IS61LV51216
512K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 8, 10, and 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 m
A
(typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
ISSI
MARCH 2005
®
DESCRIPTION
The
ISSI
IS61LV51216 is a high-speed, 8M-bit static RAM
organized as 525,288 words by 16 bits. It is fabricated using
ISSI
's high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields high-performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,
CE
and
OE.
The active LOW Write Enable
(WE) controls both writing and reading of the memory. A data
byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV51216 is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
03/10/05
1
IS61LV51216
PIN CONFIGURATIONS
48-Pin mini BGA (9mmx11mm)
PIN DESCRIPTIONS
A0-A18
1
2
3
4
5
6
ISSI
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
®
1
2
3
4
5
6
7
I/O0-I/O15
CE
OE
WE
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
VDD
I/O
14
I/O
15
A18
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
A17
GND
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
N/C
I/O
0
I/O
2
LB
UB
NC
V
DD
GND
VDD
GND
I/O
6
I/O
7
NC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter
V
TERM
V
DD
T
STG
P
T
Terminal Voltage with Respect to GND
V
DD
Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
DD
+0.5
–0.3 to +4.0
–65 to +150
1.0
Unit
V
V
°C
W
8
9
10
11
12
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
03/10/05
3
IS61LV51216
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
3.3V +10%, -5%
3.3V +10%, -5%
ISSI
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
DD
GND
≤
V
OUT
≤
V
DD
Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–5
–1
–5
Max.
—
0.4
V
DD
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
1
V
DD
Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
DD
= Max.,
Com.
I
OUT
= 0 mA, f = f
MAX
Ind.
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
Com.
Ind.
-8
Min. Max.
—
—
—
—
—
—
110
120
30
35
20
25
-10
Min. Max.
—
—
—
—
—
—
100
110
30
35
20
25
-12
Min. Max.
—
—
—
—
—
—
90
100
30
35
20
25
Unit
mA
mA
I
SB
2
V
DD
= Max.,
Com.
CE
≥
V
DD
– 0.2V,
Ind.
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
03/10/05
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