5962R8957701YC datasheet, PDF - EEWORLD Datasheet

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5962R8957701YC: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP84, 0.050 INCH PITCH, FP-84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，59 Pages; ManufacturerCobham Semiconductor Solutions

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5962R8957701YC Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP84, 0.050 INCH PITCH, FP-84

5962R8957701YC Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	QFP,
Contacts	84
Reach Compliance Code	unknow
Address bus width	16
boundary scan	NO
maximum clock frequency	12 MHz
letter of agreement	MIL-STD-1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	S-CQFP-G84
JESD-609 code	e4
length	29.21 mm
low power mode	NO
Number of serial I/Os	2
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	2.794 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	QUAD
total dose	100k Rad(Si) V
width	29.21 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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UT1553 BCRTM

EATURES

Comprehensive MIL-STD-1553 dual-redundant Bus

Controller (BC) and Remote Terminal (RT) and

Monitor (M) functions

MIL-STD-1773 compatible

Multiple message processing capability in BC

Time tagging and message logging in RT and M modes

Automatic polling and intermessage delay in

BC mode

Programmable interrupt scheme and internally

generated interrupt history list

programmability

DMA memory interface with 64K addressability

Internal self-test

Radiation-hardened option available for 84-lead

flatpack package only

Remote terminal operations in ASD/ENASD-certified

(SEAFAC)

Available in 84-pin pingrid array, 84-lead flatpack, 84-

lead leadless chip-carrier

Standard Microcircuit Drawing 5962-89577 available

- QML Q and V compliant

REGISTERS

CONTROL

HIGH-PRIORITY

STD PRIORITY LEVEL

STD PRIORITY PULSE

STATUS

CURRENT BC (or M) BLOCK/

RT DESCRIPTOR SPACE

POLLING COMPARE

CLOCK &

RESET

LOGIC

INTERRUPT

HANDLER

BC PROTOCOL

MESSAGE

HANDLER

BUILT-IN-TEST WORD

CURRENT COMMAND

INTERRUPT LOG

LIST POINTER

HIGH-PRIORITY

INTERRUPT ENABLE

HIGH-PRIORITY

INTERRUPT STATUS

STANDARD INTERRUPT

ENABLE

RT/MONITOR

PROTOCOL &

MESSAGE

HANDLER

BUILT-

IN-

TEST

RT ADDRESS

BUILT-IN-TEST

START COMMAND

RESET COMMAND

RT TIMER

RESET COMMAND

MONITOR ADDRESS

CONTROL

MONITOR ADDRESS

SELECT (0-15)

ADDRESS

MONITOR ADDRESS

SELECT (16-31)

DATA

12MHz

MASTER

RESET

1553

DATA

CHANNEL

1553

DATA

CHANNEL

DUAL

CHANNEL

ENCODER/

DECODER

MODULE

PARALLEL-

TO-SERIAL

CONVER-

SION

BUS

TRANSFER

LOGIC

SERIAL-TO-

PARALLEL

CONVER-

SION

TIMERON

TIMEOUT

ADDRESS

GENERATOR

DMA/CPU

CONTROL

DMA ARBITRATION

DUAL-PORT MEMORY CONTROL

Figure 1. BCRTM Block Diagram

BCRTM-1

Table of Contents

1.0

INTRODUCTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

1.2

1.3

2.0

3.0

4.0

5.0

Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

PIN IDENTIFICATION AND DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

INTERNAL REGISTERS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SYSTEM OVERVIEW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SYSTEM INTERFACE.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

5.2

5.3

5.4

5.6

6.0

DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

REMOTE TERMINAL ARCHITECTURE.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

6.2

6.3

7.0

BUS CONTROLLER ARCHITECTURE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1

7.2

7.3

7.4

7.5

8.0

MONITOR ARCHITECTURE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1

8.2

8.3

9.0

10.0

11.0

12.0

13.0

EXCEPTION HANDLING AND INTERRUPT LOGGING

. . . . . . . . . . . . . . . . . . . . . . . . 36

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS

. . . . . . . . . . . . . . . . 40

DC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PACKAGE OUTLINE DRAWINGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

BCRTM-2

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