SIT5186ACCFA230JH-1.000000X datasheet, PDF

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SIT5186ACCFA230JH-1.000000X: DescriptionClipped Sine Output Oscillator, 1MHz Nom,; CategoryPassive components oscillator; File Size1MB，36 Pages; ManufacturerSiTime; Environmental Compliance

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SIT5186ACCFA230JH-1.000000X Overview

Clipped Sine Output Oscillator, 1MHz Nom,

SIT5186ACCFA230JH-1.000000X Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145146086561
package instruction	LCC4,.13X.2,52/48
Reach Compliance Code	unknown
Ageing	1 PPM/FIRST YEAR
Frequency Adjustment - Mechanical	NO
frequency stability	1%
Installation features	SURFACE MOUNT
Number of terminals	10
Nominal operating frequency	1 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	CLIPPED SINE
Output impedance	10000 Ω
Output level	0.8 V
Package body material	CERAMIC
Encapsulate equivalent code	LCC10,.13X.2,58/52/48
physical size	5.15mm x 3.35mm x 1.06mm
Filter level	AEC-Q100
Maximum supply voltage	3.3 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES

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SiT5186

ADVANCED

AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO

Description

The

SiT5186 is a ±0.5 to ±2.5 ppm MEMS Super-TCXO

Features



that is engineered for best dynamic performance. It is ideal

for high reliability GNSS-based precision positioning and

timing applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5186 delivers the best dynamic performance for timing

stability in the presence of environmental stressors due to

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5186 offers three device configurations that can be

ordered using

Ordering Codes

for:



Automotive AEC-Q100 qualified

AEC-Q100 Grade 2 temp. range (-40°C to +105°C)

Grade 3 and 4 also available

Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for low lead times

Best dynamic stability under airflow, thermal shock



±0.5 ppm stability across temperature



±15 ppb/°C typical frequency slope (ΔF/ΔT)

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5V, 2.8V, 3.0V and 3.3V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications

The SiT5186 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.



Precision GNSS systems

Block Diagram

5.0 x 3.2 mm

Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5186 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 0.3

November 15, 2018

www.sitime.com

SiT5186

AEC-Q100, 1 to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 x 3.2 mm

Package Pinout..................................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 13

Typical Performance Plots ......................................................................................................................................................... 14

Architecture Overview ................................................................................................................................................................ 16

Frequency Stability ............................................................................................................................................................. 16

Output Frequency and Format............................................................................................................................................ 16

Output Frequency Tuning ................................................................................................................................................... 16

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17

Device Configurations ................................................................................................................................................................ 17

TCXO Configuration ........................................................................................................................................................... 17

VCTCXO Configuration ...................................................................................................................................................... 18

DCTCXO Configuration ...................................................................................................................................................... 19

VCTCXO-Specific Design Considerations ................................................................................................................................. 20

Linearity .............................................................................................................................................................................. 20

Control Voltage Bandwidth ................................................................................................................................................. 20

FV Characteristic Slope K

................................................................................................................................................. 20

Pull Range, Absolute Pull Range ........................................................................................................................................ 21

DCTCXO-Specific Design Considerations ................................................................................................................................. 22

Pull Range and Average Pull Range .................................................................................................................................. 22

Output Frequency ............................................................................................................................................................... 23

C Control Registers .......................................................................................................................................................... 25

Register Descriptions.......................................................................................................................................................... 25

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW)......................................... 26

[14]

....................................................................................... 27

Serial Interface Configuration Description .......................................................................................................................... 28

Serial Signal Format ........................................................................................................................................................... 28

Parallel Signal Format ........................................................................................................................................................ 29

Parallel Data Format ........................................................................................................................................................... 29

C Timing Specification ...................................................................................................................................................... 31

C Device Address Modes ................................................................................................................................................. 32

Schematic Example ............................................................................................................................................................ 33

Dimensions and Patterns ........................................................................................................................................................... 34

Layout Guidelines ...................................................................................................................................................................... 35

Manufacturing Guidelines .......................................................................................................................................................... 35

Rev 0.3

Page 3 of 36

www.sitime.com

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