SL28770
EProClock
®
Generator for Intel Calpella Chipset
Features
•
Intel CK505 Clock Revision 1.0 Compliant
• Hybrid Video Support - Simultaneous DOT96,
27MHz_SS and 27MHz_NSS video clocks
• PCI-Express Gen 2 Compliant
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Wireless friendly 3-bits slew rate control on
single-ended clocks.
• Differential CPU clocks with selectable frequency
• 100MHz Differential SRC clocks
• 100MHz Differential SATA clocks
• 96MHz Differential DOT clock
• 27MHz Video clock
• 48MHz USB clock
• Buffered Reference Clock 14.318MHz
• 14.318MHz Crystal Input or Clock input
• EProClock
®
Programmable Technology
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 32-pin QFN package
CPU
x2
SRC
x1
SATA DOT96 USB_48 REF 27M
x1
x1
x1
x1
x2
Block Diagram
Pin Configuration
CKPWRGD/ PD#
24
VDD_CPU
23
CPU0
22
CPU#0
SL28770
21
VSS_CPU
20
CPU1
19
CPU#1
18
VDD_CPU_IO
17
VDD_SRC
9 10 11 12 13 14 15 16
SRC0# / SATA#
VDD_SRC_IO
SRC0 / SATA
CPU_STP#
VSS_SRC
VSS_27
SRC1
SRC#1
REF0/ FS**
XIN/CLKIN
32 31 30 29 28 27 26 25
VDD_DOT
1
VSS_DOT
2
DOT96
3
DOT96#
4
VDD_27
5
27_NSS
6
27_SS
7
USB_48
8
** Internal 100K-ohm Pull-Down Resistor
DOC#: SP-AP-0065 (Rev. AA)
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
Page 1 of 22
www.silabs.com
VSS_REF
VDD_REF
SDATA
XOUT
SCLK
SL28770
32-QFN Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
VDD_DOT
VSS_DOT
DOT96
DOT96#
VDD_27
27M_NSS
27M_SS
USB_48
VSS_27
SRC0 / SATA
SRC0# / SATA#
VSS_SRC
SRC1
SRC1#
VDD_SRC_IO
CPU_STP#
VDD_SRC
VDD_CPU_IO
CPU1#
CPU1
VSS_CPU
CPU0#
CPU0
VDD_CPU
CKPWRGD/PD#
Type
PWR
GND
Description
3.3V Power supply for outputs and PLL
Ground for outputs
O, DIF Fixed true 96MHz clock output
O, DIF Fixed complement 96MHz clock output
PWR
O,SE
O,SE
GND
3.3V Power supply for 27MHz PLL
Non-spread 27MHz video clock output
Non-spread 48MHz video clock output
Ground for 27MHz PLL
O, SE Spread 27MHz video clock output
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
GND
Ground for PLL
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
PWR
I
PWR
PWR
Scalable 3.3V to 1.05V power supply for output buffer
3.3V tolerance input to stop the CPU clock
3.3V Power supply for PLL
Scalable 3.3V to 1.05V power supply for output buffer
O, DIF Complement differential CPU clock output
O, DIF True differential CPU clock output
GND
Ground for PLL
O, DIF Complement differential CPU clock output
O, DIF True differential CPU clock output
PWR
I
3.3V Power supply for CPU PLL
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW)
Ground for outputs
14.318MHz Crystal input or 3.3V, 14.318MHz Clock Input
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down
26
27
28
29
30
VSS_REF
XOUT
XIN/CLKIN
VDD_REF
REF/FS**
GND
I
PWR
O, SE 14.318MHz Crystal output,
Float XOUT if using only CLKIN (Clock input)
PD, I/O 3.3V tolerant input for Graphic clock selection/fixed 14.318MHz clock output.
(Internal
100K-ohm pull-down resistor on FS pin)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
I/O
I
SMBus compatible SDATA
SMBus compatible SCLOCK
31
32
SDATA
SCLK
DOC#: SP-AP-0065 (Rev. AA)
Page 2 of 22
SL28770
PC EProClock
®
Programmable Technology
PC EProClock
®
is the world’s first non-volatile programmable
PC clock. The PC EProClock
®
technology allows board
designer to promptly achieve optimum compliance and clock
signal integrity; historically, attainable typically through device
and/or board redesigns.
PC EProClock
®
technology can be configured through SMBus
or hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
Frequency Select Pin (FS)
FS
0
1
CPU
133MHz
100MHz
Power On
Default
100MHz
100MHz
96MHz
48MHz
27MHz
14.318MHz
SRC
SATA
DOT96
USB_48
27MHz
REF
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
.
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Block Read Protocol
Description
DOC#: SP-AP-0065 (Rev. AA)
Page 3 of 22
SL28770
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
36:29
37
45:38
46
....
....
....
....
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
DOC#: SP-AP-0065 (Rev. AA)
Page 4 of 22
SL28770
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
@Pup
HW
0
1
0
0
0
Name
FS
RESERVED
RESERVED
iAMT_EN
RESERVED
SRC_Main_SEL
Description
CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz
RESERVED
RESERVED
iAMT Enable
0 = Legacy Mode, 1 = iAMT Enabled
RESERVED
Select source for SRC clock
0 = SRC_MAIN = PLL1,
PLL3_CFG Table applies
1 = SRC_MAIN = PLL3,
PLL3_CFG Table does not apply
Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL4
Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
1
0
0
1
SATA_SEL
PD_Restore
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
0
0
0
1
0
1
Name
RESERVED
PLL1_SS_DC
PLL3_SS_DC
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
RESERVED
RESERVED
RESERVED
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0)
See Table 4 on page 9 for Configuration.
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
REF_OE
USB_48_OE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
Output enable for USB_48
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 3: Control Register 3
Bit
7
6
@Pup
1
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
Description
DOC#: SP-AP-0065 (Rev. AA)
Page 5 of 22
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