Integrated DeviceTechnology
Integrated DeviceTechnology
Timing Fabric for
Communications Equipment
Backplane
Timing Bus
T1/E1/J1
Dual LIU
82V2082
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IDT LINE CARD SOLUTIONS
Line Card PLL Features
• Dual PLL chip: one can be used for the transmit
path and the other for the receive path
• Programmable DPLL bandwidth
• Supports automatic hitless reference switching
• Provides a 1 PPS sync input signal and a 1 PPS
sync output signal
• Generates output clocks for Synchronous Ethernet,
SONET, SDH, GPS, 3G and GSM components
• Available in QFN, lead free packages
Jitter Attenuator Features
• FemtoClock
®
product is a frequency multiplier
and jitter attenuator component that generates
low jitter Ethernet clocks and can easily meet
10 Gigabit Ethernet requirements.
• Optimized for PDH or SONET/SDH to Ethernet
frequency translation and jitter attenuation
• Attenuates the phase jitter of the input clock
by using a low-cost pullable fundamental
mode VCXO crystal
• Available in QFN, lead-free packages
IDT TIMING CARD SOLUTIONS
IDT WAN PLL Features
• Up to 15 total inputs and 11 outputs
• IEEE-1588 Support (External DCO* control)
• 2 indpendent DPLL + APLL paths
− T0 path for node timing synchronization
− T4 path for equipment synchronization
• Frequency Range: 1 Hz to 625 MHz
• Ethernet and SONET/SDH Clocks
Phase noise <1.3 ps RMS (12 kHz to 20 MHz)
• Available in VFQFN and TQFP packages for reduced
board space
IDT T1/E1 LIU Features
• Dual and Single channel LIU devices available
• Supports Hitless Protection Switching for 1+1
protection without external relays
• Receiver sensitivity exceeds -36 dB @ 772 kHz and
-43 dB @ 1024 kHz
• Programmable T1/E1/J1 switchability allows
one bill of material for any line type
• Loss of signal (LOS) and Alarm Indication
Signal (AIS) detection
• JTAG interface
• Available in TQFP or FPBGA lead-free packages
Timing Card 1 (active)
82V3391
T0 DPLL
Active
Clock
Output
19.44MHz
1 GE Line Card
82V3395
DPLL1
DPLL2
Rx recovered ETH CLK
Tx ETH CLK
From
BITS/SSU
1G
Ethernet
PHY
To
BITS/SSU
WAN PLL
T4 DPLL
T1/E1/J1
Dual LIU
82V2082
Time Card 2 (stdby)
Timing Card 2 (stby)
82V3391
T0 DPLL
Stand By
Clo
Cloc
Clock
Outp
Output
19.44
19.44MHz
4M
10 GE Line Card
82V3395
DPLL1
DPLL2
Rx recovered ETH CLK
Tx ETH CLK
JA PLL
813N252i-02
From
BITS/SSU
10G
Ethernet
PHY
To
BITS/SSU
WAN PLL
T4 DPLL
Timing Card, 2 per box
Figure 1: Timing Fabric Architecture - Timing Cards and Line Cards
Recovered
Clocks
Line Card, 10+ per box
Figure 1 - Timing Fabric Architecture - Timing Cards and Line Cards
Architecture Overview
Communication equipment requires synchronization to transport multiple services (voice, data and video) over
Carrier networks. The Timing Fabric, as illustrated in the
Figure 1
and
Figure 2,
enables equipment such as routers,
multi-service switching platforms, PON (Passive Optical Network) and DSLAM (Digital Subscriber Line Access
Multiplexer), to meet the stringent synchronization requirements of communication networks.
The architecture in
Figure 1
segments the Timing Fabric into 2 major elements: Timing Cards and Line Cards. On
the Timing Cards, the WAN PLLs are primarily responsible for compliance with synchronization standards. The T1/
E1 LIUs receive external BITS/SSU references for the T0 DPLLs which generate standards compliant synchronous
clocks and distribute them to the backplane for the Line Cards. Recovered clocks from the Line Card PHYs are used
as references by the T4 DPLLs which rate convert them for the T1/E1 LIU transmitters that provide line references
to the external BITS/SSU. On the Line Cards DPLLs select a backplane reference from one of the Timing Cards, the
reference is rate converted and jitter attenuated to meet the needs of the specific PHYs used on these cards; for
10G applications an additional jitter attenuator may be needed. Depending on the number of PHY reference clocks
required on each Line Card a discrete fan-out buffer may also be needed. Recovered clocks from Line Card PHYs
are rate converted to a backplane frequency (8 kHz, 19.44 MHz, or 25 MHz) and sent to the backplane for the T4
DPLLs on the Timing Cards.
The architecture in
Figure 2
has the Timing Fabric in one up-link transmission card. Both the traditional Timing
Card and Line Card functionality are combined into one card. The recovered clock from the PHY is sent to the
WAN PLL for filtering, frequency translation and generation of backplane clocks. The clock generated by the
WAN PLL is filtered with a jitter attenuator and used as a transmitting clock for the PHY + Framer.
As the only supplier with all of the different timing components to provide complete solutions, IDT is uniquely
positioned to meet the needs of communication equipment suppliers and offer compelling solutions for all Timing
Fabric architectures.
• Standards Compliant WAN PLLs (EEC-Option 1, EEC-Option 2, ST3, SMC, ST4E and
ST4 (ITU-T G.8262, ITU-T G.813, GR-253-CORE, and GR1244-CORE))
• T1/E1 Dual LIUs
• Line card PLLs
• Jitter attenuators and frequency translators
• Differential fan-out buffers with low additive RMS phase jitter
• Backplane interface / translators (as needed)
IDT TRANSPORT EQUIPMENT TIMING FABRIC PRODUCT OVERVIEW
1
* DCO = Digitally Controlled Oscillator
IDT
|
THE ANALOG + DIGITAL COMPANY
POWER MANAGEMENT | ANALOG & RF |
INTERFACE & CONNECTIVITY
|
CLOCKS & TIMING
| MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO
Integrated DeviceTechnology
Timing Fabric for Communications Equipment
Clk Output
WAN PLL
Up-link Transmission Card
DSL or PON Line Card
IDT82V3398
Digital
PLL Core
Rx Clk
Tx Clk
DSL or PON Line Card
PHY +
Framer
DSL or PON Line Card
JA PLL
813N252i-02
Up-link Transmission Card, 1 to 2 per box
Figure 2 - Timing Fabric Architecture (Up-link Transmission Card)
Line Card components
Product Type
Frequency Translator & Jitter Attenuator
Frequency Translator & Jitter Attenuator
Frequency Translator & Jitter Attenuator
Frequency Translator & Jitter Attenuator
Frequency Translator & Jitter Attenuator
Part Number
849N202I
840N202I
849N212I
82V3395
# of Outputs
& Types
2 Differential
2 Differential
2 Differential
2 Differential
1 Differential,
1 Single-Ended
2 Differential
2 Single-Ended,
2 Differential,
2 Frame Sync
# of Outputs &
Types
6 Single-Ended,
3 Differential,
2 Frame Sync
4 Single-Ended,
2 Differential,
2 Frame Sync
4 Single-Ended,
2 Differential,
2 Frame Sync
Output Frequency Range
1 MHz - 1.3 GHz
1 MHz - 1.3 GHz
1 MHz - 1.3 GHz
1 MHz – 250 MHz
REF; 7.7 MHz – 875 MHz
25 MHz – 312.5 MHz
1 Hz (1PPS) - 644.53125 MHz
# of Inputs &
Types
2 (same freq)
2 (same freq)
2 (same freq)
2 (same freq)
2 (same freq)
2 (same freq)
4 Single-Ended,
2 Frame Sync
Input Frequency
Range
8 kHz – 710 MHz
8 kHz – 710 MHz
8 kHz – 710 MHz
8 kHz – 710 MHz
4 MHz – 710 MHz
8 kHz – 155.52 MHz
8 kHz – 155.52 MHz
RMS Jitter
(fs)
400 – 900
400 – 900
300 – 800
300 – 800
700
350
< 1.3 ps
Package Type
40-QFN
40-QFN
40-QFN
40-QFN
48-QFN
32-QFN
72-QFN
8T49N203I
8T49N222I
Frequency Translator & Jitter Attenuator
813N252I-09
Line card WAN PLL
Timing Card/Up-Link Transmission Card Component
Product Type
Dual Timing Card PLL
Part Number
82V3391
82V3399
82V3398
Output Frequency Range
1 Hz (1 PPS) – 644.53125 MHz
# of Inputs &
Types
Input Frequency
Range
RMS Jitter
(ps)
< 1.3
Package Type
100-TQFP
10 Single-Ended,
4 Differential, 1 Hz (1 PPS) – 625 MHz
1 Frame Sync
4 Single-Ended,
2 Differential,
2 Frame Sync
4 Single-Ended,
2 Differential,
2 Frame Sync
1 Hz (1 PPS) - 625 MHz
Dual Timing Card PLL
1 Hz (1 PPS) – 644.53125 MHz
< 1.3
72-QFN
Single Timing Card PLL
1 Hz (1 PPS) – 644.53125 MHz
1 Hz (1 PPS) - 625 MHz
< 1.3
72-QFN
T1/E1 Line Interface Unit (LIU) Solutions
Part Number
82V2081
82V2082
# of Channels
2
1
Receiver Sensitivity
-36 dB @ 772 kHz, -43 dB @ 1024 kHz
-36 dB @ 772 kHz, -43 dB @ 1024 kHz
Package Type
80-TQFP, 80-FPBGA
44-TQFP
Discover what IDT know-how can do for you @ www.IDT.com/go/clocks. For more info, contact us at clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters
of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. © Copyright 2012. All rights reserved.
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IDT TRANSPORT EQUIPMENT TIMING FABRIC PRODUCT OVERVIEW
2
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