ZL30406QGG1 datasheet, PDF - EEWORLD Datasheet

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ZL30406QGG1: DescriptionIC pll sonet/sdh clk mult 64tqfp; CategoryWireless rf/communication Telecom circuit; File Size177KB，22 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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ZL30406QGG1 Overview

IC pll sonet/sdh clk mult 64tqfp

ZL30406QGG1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	QFP
package instruction	HTFQFP,
Contacts	64
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HTFQFP
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

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ZL30406

SONET/SDH Clock Multiplier PLL

Data Sheet

Features

•

Meets jitter requirements of Telcordia GR-253-

CORE for OC-48, OC-12, and OC-3 rates

Meets jitter requirements of ITU-T G.813 for STM-

16, STM-4 and STM-1 rates

Provides four LVPECL differential output clocks at

77.76 MHz

Provides a CML differential clock programmable

to 19.44 MHz, 38.88 MHz, 77.76 MHz and

155.52 MHz

Provides a single-ended CMOS clock at

19.44 MHz

Provides enable/disable control of output clocks

Accepts a CMOS reference at 19.44 MHz

3.3 V supply

ZL30406QGG1

July 2011

Ordering Information

64 Pin TQFP*

Trays, Bake & Drypack

*Pb Free Matte Tin

-40C to +85C

Description

The ZL30406 is an analog phase-locked loop (APLL)

designed to provide rate conversion and jitter

attenuation for SDH (Synchronous Digital Hierarchy)

and SONET (Synchronous Optical Network)

networking equipment. The ZL30406 generates very

low jitter clocks that meet the jitter requirements of

Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1

rates and ITU-T G.813 STM-16, STM-4 and STM-1

rates.

The ZL30406 accepts a CMOS compatible reference

at 19.44 MHz and generates four LVPECL differential

output clocks at 77.76 MHz, a CML differential

clock programmable to 19.44 MHz, 38.88 MHz,

77.76 MHz and 155.52 MHz and a single-ended

CMOS clock at 19.44 MHz. The output clocks can

be individually enabled or disabled.

•

Applications

•

SONET/SDH line cards

Network Element timing cards

LPF

C77oEN-A

C77oEN-B

OC-CLKoEN

C77o

C155o

C19o, C38o,

CML-P/N outputs

OC-CLKoP/N

C19i

Frequency

& Phase

Detector

19.44MHz

C77oP/N-D

BIAS

Reference &

Bias circuit

Loop

Filter

Output

VCO

C77oP/N-A

C77oP/N-B

C77oP/N-C

Interface

Circuit

C19o

VDD GND

VCC

FS1-2

C19oEN

C77oEN-C

C77oEN-D

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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