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SI5330B-A00205-GM

Description
IC clk buffer 1:4 710mhz 24qfn
Categorylogic    logic   
File Size137KB,20 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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SI5330B-A00205-GM Overview

IC clk buffer 1:4 710mhz 24qfn

SI5330B-A00205-GM Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeQFN
package instructionHVQCCN, LCC24,.16SQ,20
Contacts24
Reach Compliance Codeunknow
series5330
Input adjustmentDIFFERENTIAL
JESD-30 codeS-XQCC-N24
length4 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
MaximumI(ol)0.004 A
Number of functions1
Number of inverted outputs
Number of terminals24
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-DRAIN
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC24,.16SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8/3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.1 ns
Maximum seat height0.9 mm
Maximum supply voltage (Vsup)2.75 V
Minimum supply voltage (Vsup)2.25 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width4 mm
minfmax710 MHz
Si5330
1 . 8 / 2 . 5 / 3 . 3 V L
O W
- J
I T T E R
, L
O W
- S
K EW
C
L O C K
B
U F F E R
/ L
E V E L
T
R A N S L A T O R
Features
18
17
16
15
14
13
7
8
9
10
11
12
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation

Differential to single-ended

Single-ended to differential

Differential to differential

Single-ended to single-ended
Wide frequency range

LVPECL, LVDS: 5 to 710 MHz

HCSL: 5 to 250 MHz

SSTL, HSTL: 5 to 350 MHz

CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
RSVD_GND
CLK0A
CLK0B
VDD
VDDO0
20
Small size: 24-lead, 4 x 4 mm
QFN
24
23
22
21
19
OEB
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
RSVD_GND
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85
°
C
Ordering Information:
See page 14.
Pin Assignments
IN1
IN2
IN3
1
Applications
2
3
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
RSVD_GND
RSVD_GND
RSVD_GND
GND
GND
CLK3B
Functional Block Diagram
V
DD
V
DDO0
CLK0
Si5330
V
DDO1
CLK1
Single-ended
or
Differential
IN
V
DDO2
CLK2
Single-ended
or
Differential
V
DDO3
LOS
OEB
Control
CLK3
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
VDDO3
VDD
LOS
CLK3A
4
5
6
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