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8S73034AMILF

Description
IC divider lvpecl 16-soic
Categorysemiconductor    Analog mixed-signal IC   
File Size803KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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IC divider lvpecl 16-soic

8S73034AMILF Parametric

Parameter NameAttribute value
Datasheets
ICS8S73034
Product Photos
16 SOIC
PCN Design/Specificati
Assembly Lot Number Scheme 12/Oct/2013
Standard Package48
CategoryIntegrated Circuits (ICs)
FamilyClock/Timing - Clock Generators, PLLs, Frequency Synthesizers
PackagingTube
TypeClock Divide
PLLN
InpuCML, LVDS, LVPECL, SSTL
OutpuLVPECL
Number of Circuits1
Ratio - InpuOutpu
Differential - InpuOutpu
Frequency - Max1.6GHz
Divider/MultiplieYes/N
Voltage - Supply2.375 V ~ 3.8 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mou
Package / Case16-SOIC (0.154", 3.90mm Width)
Supplier Device Package16-SOIC
Other NamesICS8S73034AMILFICS8S73034AMILF-ND
Low Skew,
÷
2
, ÷
4
, ÷
8 Differential-to-LVPECL
Clock Divider
ICS8S73034I
DATA SHEET
General Description
The ICS8S73034I is a high-speed, differential-to- LVPECL clock
divider designed for high-performance telecommunication,
computing and networking applications. High clock frequency
capability and the differential design make the ICS8S73034I an ideal
choice for performance clock distribution networks. The device
frequency-divides the input clock by ÷2, ÷4 and ÷8. Each
frequency-divided clock signal is output at a separate LVPECL
output. The differential input pair can be driven by LVPECL, LVDS,
CML and SSTL signals. Single-ended input signals are supported by
using the integrated bias voltage generator (V
BB
). The ICS8S73034I
is optimized for 3.3V and 2.5V power supply voltages and the
temperature range of -40 to +85°C. The device is available in
space-saving 16-lead TSSOP and SOIC packages.
Features
÷2, ÷4 and ÷8 clock frequency divider
Three differential LVPECL output pairs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML
V
BB
bias voltage generator supports single-ended LVPECL clock
input signals
LVCMOS control inputs
Maximum input frequency: 3.2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with bias resistors on nPCLK input
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nEN
Pulldown
Pin Assignment
D
Q
LE
÷2
R
÷4
R
Q1
nQ1
Q0
nQ0
Q0
nQ0
V
CC
Q1
nQ1
V
CC
Q2
nQ2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
nEN
nc
PCLK
nPCLK
V
BB
MR
V
EE
PCLK
Pulldown
nPCLK
Pullup/Pulldown
VBB
÷8
R
MR
Pulldown
Q2
nQ2
ICS8S73034I
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.375mm package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS8S73034AMI REVISION A JUNE 8, 2011
1
©2011 Integrated Device Technology, Inc.

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