Low Skew,
÷
2
, ÷
4
, ÷
8 Differential-to-LVPECL
Clock Divider
ICS8S73034I
DATA SHEET
General Description
The ICS8S73034I is a high-speed, differential-to- LVPECL clock
divider designed for high-performance telecommunication,
computing and networking applications. High clock frequency
capability and the differential design make the ICS8S73034I an ideal
choice for performance clock distribution networks. The device
frequency-divides the input clock by ÷2, ÷4 and ÷8. Each
frequency-divided clock signal is output at a separate LVPECL
output. The differential input pair can be driven by LVPECL, LVDS,
CML and SSTL signals. Single-ended input signals are supported by
using the integrated bias voltage generator (V
BB
). The ICS8S73034I
is optimized for 3.3V and 2.5V power supply voltages and the
temperature range of -40 to +85°C. The device is available in
space-saving 16-lead TSSOP and SOIC packages.
Features
•
•
•
•
•
•
•
•
•
•
•
÷2, ÷4 and ÷8 clock frequency divider
Three differential LVPECL output pairs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML
V
BB
bias voltage generator supports single-ended LVPECL clock
input signals
LVCMOS control inputs
Maximum input frequency: 3.2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with bias resistors on nPCLK input
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nEN
Pulldown
Pin Assignment
D
Q
LE
÷2
R
÷4
R
Q1
nQ1
Q0
nQ0
Q0
nQ0
V
CC
Q1
nQ1
V
CC
Q2
nQ2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
nEN
nc
PCLK
nPCLK
V
BB
MR
V
EE
PCLK
Pulldown
nPCLK
Pullup/Pulldown
VBB
÷8
R
MR
Pulldown
Q2
nQ2
ICS8S73034I
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.375mm package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS8S73034AMI REVISION A JUNE 8, 2011
1
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Table 1. Pin Descriptions
Number
1, 2
3, 6, 16
4, 5
7, 8
9
Name
Q0, nQ0
V
CC
Q1, nQ1
Q2, nQ2
V
EE
MR
Output
Power
Output
Output
Power
Type
Description
Differential output pair. LVPECL interface levels.
Power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Bias voltage.
Pullup/
Pulldown
Pulldown
Inverting differential clock input. Defaults to
2
/
3
* V
CC
when left open.
LVPECL interface levels.
Non-inverting differential clock input. LVPECL interface levels.
No connect.
Pulldown
Synchronous clock enable. When logic LOW, the clock is enabled and
frequency-divided. When logic HIGH, the clock is disabled and the outputs remain
stopped in the same logic state (hold). LVTTL / LVCMOS interface levels.
10
Input
Pulldown
11
12
13
14
15
V
BB
nPCLK
PCLK
nc
nEN
Output
Input
Input
Unused
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
75
37.5
Maximum
Units
k
Ω
k
Ω
Function Table
Table 3. Truth Table
Inputs
PCLK
↓
↑
X
nEN
L
H
X
MR
L
L
H
Function
Divide
Hold Q[0:2]
Reset Q[0:2]
↑
= Rising edge transition
↓
= Falling edge transition
X = Don’t care
ICS8S73034AMI REVISION A JUNE 8, 2011
2
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
(LVPECL mode)
Outputs, I
O
Continuos Current
Surge Current
V
BB
Sink/Source, I
BB
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
16 Lead SOIC, Junction-to-Ambient
16 Lead TSSOP, Junction-to-Ambient
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-0.5V to V
CC
+ 0.5V
50mA
100mA
±0.5mA
-40°C to +85°C
70.2°C/W (0 mps)
100°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
45
Units
V
mA
ICS8S73034AMI REVISION A JUNE 8, 2011
3
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Table 4B. DC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V; T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
Parameter
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Units
Output High
Voltage; NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage
(Single-ended)
Input Low Voltage
(Single-ended)
Output Voltage
Reference
V
CC
-1.070
V
CC
-1.960
0.7V
CC
-0.3
V
CC
- 1.44
0.15
V
CC
-0.867
V
CC
-1.780
V
CC
-0.635
V
CC
-1.590
V
CC
+ 0.3
0.3V
CC
V
CC
- 1.32
V
CC
-1.070
V
CC
-1.960
0.7V
CC
-0.3
V
CC
- 1.44
0.15
V
CC
-0.867
V
CC
-1.780
V
CC
-0.635
V
CC
-1.590
V
CC
+ 0.3
0.3V
CC
V
CC
- 1.32
V
CC
-1.070
V
CC
-1.960
0.7V
CC
-0.3
V
CC
- 1.44
0.15
V
CC
-0.867
V
CC
-1.780
V
CC
-0.635
V
CC
-1.590
V
CC
+ 0.3
0.3V
CC
V
CC
- 1.32
V
V
V
V
V
V
V
OL
V
IH
V
IL
V
BB
V
PP
Peak-to-Peak Input
Voltage
Input High Voltage
Common Mode
Range; NOTE 2
Input
PCLK/
High
nPCLK,
Current MR, nEN
PCLK,
Input
MR, nEN
Low
Current nPCLK
0.8
1.3
0.8
1.3
0.8
1.3
V
CMR
1.2
V
CC
1.2
V
CC
1.2
V
CC
V
I
IH
150
150
150
µA
-10
-150
-10
-150
-10
-150
µA
µA
I
IL
NOTE Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
ICS8S73034AMI REVISION A JUNE 8, 2011
4
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 2.375V to 3.8V, V
EE
= 0V; T
A
= -40°C to 85°C
-40°C
Symbol
f
IN
Parameter
Input Frequency
Q0, nQ0
f
OUT
Output
Frequency
Q1, nQ1
Q2, nQ2
t
PD
tsk(o)
t
RR
t
S
t
H
t
R
/ t
F
odc
Propagation Delay; NOTE 1
Output Skew; NOTE 2
Set/Reset Recovery
Setup Time
Hold Time
Output
Rise/Fall Time
nEN
nEN
20% to 80%
80
48
145
320
270
370
Min
Typ
Max
3.2
1.6
800
400
470
50
500
400
200
210
52
85
48
150
320
310
410
Min
25°C
Typ
Max
3.2
1.6
800
400
510
50
500
400
200
215
52
100
48
165
320
330
450
Min
85°C
Typ
Max
3.2
1.6
800
400
565
50
500
400
200
230
52
Units
GHz
GHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters are measured at f
IN
≤
1.5GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Output skew at coincident rising edges.
ICS8S73034AMI REVISION A JUNE 8, 2011
5
©2011 Integrated Device Technology, Inc.
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