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SL28504BZC-2T

Description
IC clock gen eaglelake 56tssop
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size376KB,28 Pages
ManufacturerSilicon Laboratories Inc
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SL28504BZC-2T Overview

IC clock gen eaglelake 56tssop

SL28504BZC-2T Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts56
Reach Compliance Codeunknow
ECCN codeEAR99
JESD-30 codeR-PDSO-G56
length13.9 mm
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency400 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Master clock/crystal nominal frequency14.318 MHz
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
width6 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
SL28504-2
Clock Generator for Intel
®
Eaglelake Chipset
Features
• Compliant to Intel
®
CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
• 33 MHz PCI clock
CPU
x2 / x3
SRC
x8/x11
PCI
x6
REF
x2
DOT96
x1
USB_48
x1
24.576M
x1
25M
x2
• 25MHz Free run for WOL
• Selectable 25MHz/24.576MHz output
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 56-pin TSSOP packages
Block Diagram
Xin
Xout
Pin Configuration
REF0
14.318MHz
Crystal
PLL Reference
CPU[1:0]
PLL1
Divider
SRC8/CPU2_ITP
PCI[4:0]; PCIF0
PLL3
Divider
SRC
SRC_SATA
25M0_F
PLL4
Divider
25M1_24.576M
PLL2
DOT96/SRC0
Divider
USB_48
PCI_0/ CR#_A
VDD_PCI
PCI_1/ CR#_B
PCI_2
PCI_3
PCI_4 / SRC5_EN
PCIF_0 / ITP_EN
VSS_PCI
VDD_48
USB_48 / FSA
VSS_48
VDD_IO
SRC0 / DOT96
SRC0# / DOT96#
VSS_IO
VDD_PLL3
SRC1/25M0_F
SRC1#/25M1_24.576M
VSS_PLL3
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
SRC3/ CR#_C
SRC3#/ CR#_D
VDD_SRC_IO
SRC4
SRC4#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SL28504-2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB / TEST_MODE
CK_PWRGD / PWRDWN#
VDD_CPU
CPU0
CPU0#
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
*SEL_24.576M
SRC8 / CPU2_ITP
SRC8# / CPU2_ITP#
VDD_SRC_IO
SRC7/ CR#_F
SRC7#/ CR#_E
VSS_SRC
SRC6
SRC6#
VDD_SRC
SRC5/ PCI_STOP#
SRC5#/ CPU_STOP#
SATA_SEL
CK_PWRGD/PD#
SDATA
SCLK
Control Logic
PCI_STOP#
CPU_STOP#
FSC:A]
SEL_24.576M
* Internal Pull-Down
........................ DOC #: SP-AP-0051 (Rev. AA) Page 1 of 27
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com

SL28504BZC-2T Related Products

SL28504BZC-2T SL28504BZC-2 SL28504BZI-2 SL28504BZI-2T
Description IC clock gen eaglelake 56tssop IC clock gen eaglelake 56tssop IC clock gen eaglelake 56tssop IC clock gen eaglelake 56tssop
Maker Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc
Parts packaging code TSSOP TSSOP TSSOP TSSOP
package instruction TSSOP, TSSOP, TSSOP, 6 X 12 MM, LEAD FREE, MO-153EE, TSSOP-56
Contacts 56 56 56 56
Reach Compliance Code unknow unknow unknow unknow
ECCN code EAR99 EAR99 EAR99 EAR99
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
length 13.9 mm 13.9 mm 14 mm 14 mm
Number of terminals 56 56 56 56
Maximum operating temperature 70 °C 70 °C 85 °C 85 °C
Maximum output clock frequency 400 MHz 400 MHz 400 MHz 400 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency 14.318 MHz 14.318 MHz 14.31818 MHz 14.31818 MHz
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.1 mm 1.2 mm 1.2 mm
Maximum supply voltage 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.5 mm
Terminal location DUAL DUAL DUAL DUAL
width 6 mm 6 mm 6.1 mm 6.1 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC
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