SL28504-2
Clock Generator for Intel
®
Eaglelake Chipset
Features
• Compliant to Intel
®
CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
• 33 MHz PCI clock
CPU
x2 / x3
SRC
x8/x11
PCI
x6
REF
x2
DOT96
x1
USB_48
x1
24.576M
x1
25M
x2
• 25MHz Free run for WOL
• Selectable 25MHz/24.576MHz output
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 56-pin TSSOP packages
Block Diagram
Xin
Xout
Pin Configuration
REF0
14.318MHz
Crystal
PLL Reference
CPU[1:0]
PLL1
Divider
SRC8/CPU2_ITP
PCI[4:0]; PCIF0
PLL3
Divider
SRC
SRC_SATA
25M0_F
PLL4
Divider
25M1_24.576M
PLL2
DOT96/SRC0
Divider
USB_48
PCI_0/ CR#_A
VDD_PCI
PCI_1/ CR#_B
PCI_2
PCI_3
PCI_4 / SRC5_EN
PCIF_0 / ITP_EN
VSS_PCI
VDD_48
USB_48 / FSA
VSS_48
VDD_IO
SRC0 / DOT96
SRC0# / DOT96#
VSS_IO
VDD_PLL3
SRC1/25M0_F
SRC1#/25M1_24.576M
VSS_PLL3
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
SRC3/ CR#_C
SRC3#/ CR#_D
VDD_SRC_IO
SRC4
SRC4#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SL28504-2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB / TEST_MODE
CK_PWRGD / PWRDWN#
VDD_CPU
CPU0
CPU0#
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
*SEL_24.576M
SRC8 / CPU2_ITP
SRC8# / CPU2_ITP#
VDD_SRC_IO
SRC7/ CR#_F
SRC7#/ CR#_E
VSS_SRC
SRC6
SRC6#
VDD_SRC
SRC5/ PCI_STOP#
SRC5#/ CPU_STOP#
SATA_SEL
CK_PWRGD/PD#
SDATA
SCLK
Control Logic
PCI_STOP#
CPU_STOP#
FSC:A]
SEL_24.576M
* Internal Pull-Down
........................ DOC #: SP-AP-0051 (Rev. AA) Page 1 of 27
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL28504-2
56-TSSOP Pin Definitions
Pin No.
Name
1
PCI_0/ CR#_A
2
3
4
5
6
VDD_PCI
PCI_1/ CR#_B
PCI_2
PCI_3
PCI4 /SRC5_EN
Type
Description
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI_0
PWR
3.3V Power supply for PCI PLL.
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI_1.
O, SE 33 MHz clock.
O, SE, 33 MHz clock.
I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable
(Sampled on CKPWRGD assertion)
1 = SRC5, 0 =CPU_STOP#/PCI_STOP#
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
GND
PWR
I/O
GND
PWR
Ground for outputs.
3.3V Power supply for outputs and PLL.
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer
to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
3.3V-1.05V Power supply for outputs.
7
PCIF_0/ITP_EN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VSS_PCI
VDD_48
USB_48/FSA
VSS_48
VDD_IO
SRC0/DOT96T
SRC0#/DOT96#
VSS_IO
VDD_PLL3
SRC1/25M0_F
SRC1#/25M1_24.576M
VSS_PLL3
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
SRC3/ CR#_C
SRC3#/ CR#_D
VDD_SRC_IO
SRC4
SRC4#
CPU_STOP#/SRC5#
PCI_STOP#/SRC5
VDD_SRC
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
GND
PWR
Ground for PLL2.
3.3V Power supply for PLL3
O, SE 100 MHz Differential serial reference clocks/ Free run 25MHz clock output
O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock
output
GND
PWR
Ground for PLL3.
3.3V-1.05V power supply for PLL3
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND
I/O,
Dif
I/O,
Dif
PWR
Ground for outputs.
100-MHz Differential serial reference clocks / 3.3V CR#_C, input, mappable via
I2C to control either SRC 0 or SRC 2. Default SRC3
100-MHz Differential serial reference clocks / 3.3V CR#_D input, mappable via I2C
to control either SRC 1 or SRC 4. Default SRC3
3.3V-1.05V power supply for SRC outputs.
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
I/O,
Dif
I/O,
Dif
PWR
3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
clocks. The option is selected by SRC5_EN
3.3V tolerant input for stopping PCI and SRC outputs./100 MHz Differential serial
reference clocks.The option is selected by SRC5_EN
3.3V Power supply for SRC PLL.
........................ DOC #: SP-AP-0051 (Rev. AA) Page 2 of 27
SL28504-2
56-TSSOP Pin Definitions
Pin No.
32
SRC6#
33
34
35
36
37
38
SRC6
VSS_SRC
SRC7#/ CR#_E
SRC7/ CR#_F
VDD_SRC_IO
SRC8#/CPUC2_ITP#
Name
Type
Description
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND
I/O,
Dif
I/O,
Dif
PWR
Ground for outputs.
100 MHz Differential serial reference clocks/3.3V CR#_E Input controlling SRC6.
Default SRC7.
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Default SRC7.
3.3V-1.05V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
39
SRC8/CPUT2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
40
41
42
43
44
45
46
47
48
SEL_24.576M
VDD_CPU_IO
CPU1#
CPU1
VSS_CPU
CPU0#
CPU0
VDD_CPU
CK_PWRGD/PWRDWN#
I, PD
PWR
Select 25M1_24.576M output and SRC1
0 = 25M1, M= SRC1, 1 = 24.576M
3.3V-1.05V power supply for CPU outputs.
on the configuration set in Byte 11 Bit3:2.
O, DIF Differential CPU clock outputs.
Note: CPU1 is an iAMT clock in iAMT mode depending
O, DIF Differential CPU clock outputs.
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
GND
Ground for outputs.
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
14.318 MHz Crystal input.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to V
IHFS_C
when CK_PWRGD is asserted HIGH.
Refer to DC
Electrical Specifications table for
V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
49
FSB/TEST_MODE
I
50
51
52
53
54
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF0/FSC/TEST_SEL
GND
I
PWR
I/O
O, SE 14.318 MHz Crystal output.
55
56
SMB_DATA
SMB_CLK
I/O
I
........................ DOC #: SP-AP-0051 (Rev. AA) Page 3 of 27
SL28504-2
Frequency Select Pin (FSA, FSB and FSC)
FSC
0
0
0
0
1
1
1
1
FSB
0
0
1
1
0
0
1
1
FSA
0
1
0
1
0
1
0
1
CPU
266 MHz
133 MHz
200 MHz
166 MHz
333 MHz
100 MHz
400 MHz
Reserved
Reserved
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
SRC
PCIF/PCI
REF
DOT96
USB
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
.
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Block Read Protocol
Description
........................ DOC #: SP-AP-0051 (Rev. AA) Page 4 of 27
SL28504-2
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
46
....
....
....
....
Description
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Bit
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
........................ DOC #: SP-AP-0051 (Rev. AA) Page 5 of 27
京公网安备 11010802033920号
EEWORLD
