PI6C48535-11B
3.3V Low Jitter 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Features
•
•
•
•
•
•
•
•
•
•
•
•
Maximum output frequency: 500MHz
4 pair of differential LVPECL outputs
Selectable CLK and crystal inputs
CLK accepts LVCMOS, LVTTL input level
Ultra low additive phase jitter: < 0.05 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range)
Output Skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 1.5ns (maximum)
3.3V power supply
Pin-to-pin compatible to ICS8535-11, ICS8535-31
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green available):
- 20-pin TSSOP (L)
Description
The PI6C48535-11B is a high-performance low jitter and low-skew
LVPECL fanout buffer. PI6C48535-11B features selectable of
single-ended clock or crystal inputs and translates to four LVPECL
outputs. The CLK input accepts LVCMOS or LVTTL signals. The
outputs are synchronized with input clock during asynchronous as-
sertion /deassertion of CLK_EN pin. PI6C48535-11B is ideal for
crystal or LVCMOS/LVTTL to LVPECL translation. Typical clock
translation and distribution applications are data-communications
and telecommunications.
Block Diagram
CLK_EN
D
Q
LE
CLK
Xtal1
Xtal2
0
1
Q
0
n
Q
0
Q
1
n
Q
1
Q
2
n
Q
2
Q
3
n
Q
3
Pin Diagram
V
EE
CLK_EN
CLK_SEL
CLK
NC
Xtal
1
Xtal
2
NC
NC
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
0
N
Q
0
V
DD
Q
1
N
Q
1
Q
2
N
Q
2
V
DD
Q
3
N
Q
3
CLK_SEL
12-0203
1
www.pericom.com
PI6C48535-11B Rev A
06/01/12
PI6C48535-11B
3.3V Low Jitter 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Pin Description
Name
V
EE
CLK_EN
CLK_SEL
CLK
Xtal1,
Xtal2
NC
V
DD
Q
3
,
n
Q
3
Q
2
, nQ2
Q
1
,
n
Q
1
Q
0
,
n
Q
0
Pin #
1
2
3
4
6, 7
5, 8, 9
10, 13,
18
11, 12
14, 15
16, 17
19, 20
P
O
O
O
O
Type
P
I_PU
I_PD
I_PD
Connect to Negative power supply
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Q
x
outputs are forced low,
n
Q
x
outputs are forced high. LVCMOS/LVTTL level with 50KΩ
pull up.
Clock select input. When high, selects Xtal (Xtal1, Xtal2) inputs. When low, selects CLK
input. LVCMOS/LVTTL level with 50KΩ pull down.
LVCMOS / LVTTL clock input
Crystal input and output
No internal connection.
Connect to 3.3V
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Description
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
C
IN
R_pullup
R_pulldown
Parameter
Input Capacitance
Input Pullup Resistance
Input Pulldown Resistance
50
50
Conditions
Min.
Typ.
Max.
4
Units
pF
KΩ
KΩ
Control Input Function Table
Inputs
CLK_EN
0
0
1
1
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
Outputs
Selected Source
CLK
Xtal1, Xtal2
CLK
Xtal1, Xtal2
Q
0
:Q
3
Diasbled: Low
Disabled: Low
Enabled
Enabled
n
Q
0
:
n
Q
3
CLK_SEL
0
1
0
1
Diasbled: High
Disabled: High
Enabled
Enabled
12-0203
2
www.pericom.com
PI6C48535-11B Rev A
06/01/12
PI6C48535-11B
3.3V Low Jitter 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
Enabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Clock Input Function Table
Inputs
CLK
0
1
Q
0
:Q
3
LOW
HIGH
Outputs
n
Q
0
:
n
Q
3
HIGH
LOW
Absolute Maximum Ratings
Symbol
V
DD
V
IN
V
OUT
T
STG
Parameter
Supply voltage
Input voltage
Output voltage
Storage temperature
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
Min.
Typ.
Max.
4.6
V
DD
+0.5V
V
DD
+0.5V
150
V
o
C
Units
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci-
fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
V
DD
T
A
I
DD
Parameter
Power Supply Voltage
Ambient Temperature
Power Supply Current
All outputs unloaded
Conditions
Min.
3.135
-40
Typ.
3.3
Max.
3.465
85
130
Units
V
o
C
mA
12-0203
3
www.pericom.com
PI6C48535-11B Rev A
06/01/12
PI6C48535-11B
3.3V Low Jitter 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
LVCMOS/LVTTL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
DD
= 3.3V ± 5% unless otherwise stated below.)
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
CLK, CLK_SEL
CLK_EN
CLK, CLK_SEL
CLK_EN
V
IN
= V
DD
= 3.3V
V
IN
= V
DD
= 3.3V
V
IN
= 0V, V
DD
= 3.3V
V
IN
= 0V, V
DD
= 3.3V
-10
-150
Conditions
Min
2
-0.3
Typ
Max
V
DD
+0.3
0.8
150
10
µA
Units
V
LVPECL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
DD
= 3.3V unless otherwise stated below.)
Symbol
V
OH
V
OL
Parameter
Output High Voltage
Output Low Voltage
Conditions
Min.
2.1
1.3
Typ.
Max.
2.6
1.8
Units
V
Crystal Characteristics
Parameter
Mode of Oscillation
Frequency Range
Equivalent Series Resistance (ESR)
Shunt Capacitance
12
Min.
Typ.
Fundamental
40
70
7
MHz
Ω
pF
Max.
Units
AC Characteristics
(T
A
= -40
o
C to 85
o
C, V
DD
=
3.3V ± 5%
)
Symbol
f
max
t
jit
V
SWING
t
Pd
Tsk(o)
Tsk(pp)
t
r
/t
f
odc
Osc
Parameter
Output Frequency
Buffer Additive Jitter RMS
Peak-to-peak Output Voltage
Swing
Propagation Delay
(1) (4)
Output-to-output Skew
(2) (4)
Part-to-part Skew
(3) (4)
Output Rise/Fall time
(4)
Output duty cycle
(4)
Crystal Tolerance
20% - 80%
100
48
156.25MHz
156.25MHz
0.6
0.05
1.1
1.5
30
200
400
52
1000
%
ppm
ps
Conditions
Min.
Typ.
Max.
500
Units
MHz
ps
V
ns
Notes:
1. Measured from the V
DD
/2 of the input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point.
3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the out-
puts differential crossing point.
4. All parameters are measured with CMOS input of 266MHz unless stated otherwise
12-0203
4
www.pericom.com
PI6C48535-11B Rev A
06/01/12
PI6C48535-11B
3.3V Low Jitter 1-to-4
Crystal/LVCMOS to LVPECL Fanout Buffer
Packaging Mechanical: 20-Pin TSSOP (L)
DATE: 05/03/12
DESCRIPTION: 20-pin, 173mil Wide TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1311
REVISION: F
Notes:
1. Refer JEDEC MO-153F/AC
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
12-0373
Ordering Information
Ordering Code
PI6C48535-11BLIE
Package Code
L
Package Description
Pb-free & Green 20-pin 173-mil wide TSSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
12-0203
5
www.pericom.com
PI6C48535-11B Rev A
06/01/12
Microcontroller MCU
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