MC68EC030FE40C datasheet, PDF - EEWORLD Datasheet

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MC68EC030FE40C: DescriptionIC mpu 32bit enhanced 132-cqfp; Categorysemiconductor The embedded processor and controller; File Size394KB，36 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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IC mpu 32bit enhanced 132-cqfp

MC68EC030FE40C Parametric

Parameter Name	Attribute value
Datasheets
MC68EC030 Technical Summary
MC68030EC
Product Photos
MC68EC030FE25C
Standard Package	36
Category	Integrated Circuits (ICs)
Family	Embedded - Microprocessors
Packaging	Tray
Core Process	68030
Number of Cores/Bus Width	1 Core, 32-Bi
Speed	40MHz
Co-Processors/DSP	-
RAM Controllers	-
Graphics Accelerati	N
Display & Interface Controllers	-
Etherne	-
SATA	-
USB	-
Voltage - I/O	5.0V
Operating Temperature	0°C ~ 70°C
Security Features	-
Package / Case	132-BCQFP
Supplier Device Package	132-CQFP (24x24)
Additional Interfaces	SCI, SPI

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Freescale Semiconductor, Inc.

MOTOROLA

Order this document

by MC68EC030/D

SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded

Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for

the requirements of embedded control applications. The MC68EC030 is optimized to maintain

performance while using cost-effective memory subsystems. The rich instruction set and addressing

mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear

migration path for M68000 systems. The main features of the MC68EC030 are as follows:

•

Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

Burst-Mode Bus Interface for Efficient DRAM Access

On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

Freescale Semiconductor, Inc...

Additional features of the MC68EC030 include:

•

Complete 32-Bit Nonmultiplexed Address and Data Buses

Sixteen 32-Bit General-Purpose Data and Address Registers

Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

Pipelined Architecture with Increased Parallelism Allows:

– Internal Caches Accesses in Parallel with Bus Transfers

– Overlapped Instruction Execution

Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),

Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

Complete Support for Coprocessors with the M68000 Coprocessor Interface

Internal Status Indication for Hardware Emulation Support

4-Gbyte Direct Addressing Range

Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density

NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

•

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

For More Information On This Product,

Go to: www.freescale.com

µ MOTOROLA

Rev. 1

Freescale Semiconductor, Inc.

INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer

unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on

one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the

32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor

interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated

controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with

accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030

as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from

external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to

the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four

long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can

reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used

to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the

average access time for operand fetches is minimized.

The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)

memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the

MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating

system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

Freescale Semiconductor, Inc...

20 MHz

OSC.

MC88916

MC68EC030

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

(40 MHz)

BUS CLOCK

(80 MHz)

Figure 1.

MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the

autonomous nature of these blocks. The bus controller consists of the address and data pads, the

multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus

cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.

Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the

micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

MC68EC030 TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

MC68EC030FE40C Related Products

	MC68EC030FE40C	MC68EC030FE25C	MC68EC030CFE25C	MC68EC030FE25CB1
Description	IC mpu 32bit enhanced 132-cqfp	IC mpu 32 bit enhanced 132-cqfp	IC mpu 32bit enh 25mhz 132-cqfp	IC mpu 32bit enh 25mhz 132-cqfp
Standard Package	36	36	36	180
Category	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)
Family	Embedded - Microprocessors	Embedded - Microprocessors	Embedded - Microprocessors	Embedded - Microprocessors
Packaging	Tray	Tray	Tray	Tray
Core Process	68030	68030	68030	68030
Number of Cores/Bus Width	1 Core, 32-Bi	1 Core, 32-Bi	1 Core, 32-Bi	1 Core, 32-Bi
Speed	40MHz	25MHz	25MHz	25MHz
Graphics Accelerati	N	N	N	N
Voltage - I/O	5.0V	5.0V	5.0V	5.0V
Operating Temperature	0°C ~ 70°C	0°C ~ 70°C	-40°C ~ 85°C	0°C ~ 70°C
Package / Case	132-BCQFP	132-BCQFP	132-BCQFP	132-BCQFP
Supplier Device Package	132-CQFP (24x24)	132-CQFP (24x24)	132-CQFP (24x24)	132-CQFP (24x24)
Additional Interfaces	SCI, SPI	SCI, SPI	SCI, SPI	SCI, SPI

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