KMC68MH360RC33L datasheet, PDF

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KMC68MH360RC33L: DescriptionIC mpu quicc 33mhz 241-pga; Categorysemiconductor The embedded processor and controller; File Size572KB，14 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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KMC68MH360RC33L Overview

IC mpu quicc 33mhz 241-pga

KMC68MH360RC33L Parametric

Parameter Name	Attribute value
Datasheets
MC68360 Product Brief
Standard Package	2
Category	Integrated Circuits (ICs)
Family	Embedded - Microprocessors
Packaging	Tray
Core Process	CPU32+
Number of Cores/Bus Width	1 Core, 32-Bi
Speed	33MHz
Co-Processors/DSP	Communications
CPM
RAM Controllers	DRAM
Graphics Accelerati	N
Display & Interface Controllers	-
Etherne	10 Mbps (1)
SATA	-
USB	-
Voltage - I/O	5.0V
Operating Temperature	0°C ~ 70°C
Security Features	-
Package / Case	241-BEPGA
Supplier Device Package	241-PGA (47.24x47.24)
Additional Interfaces	SCC, SMC, SPI

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Freescale Semiconductor

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by MC68360D

MC68360

Product Brief

MC68360 QUad Integrated Communication

Controller (QUICC

™

)

Freescale Semiconductor, Inc...

INTRODUCTION

The MC68360 QUad Integrated Communication Controller (QUICC

™

) is a versatile one-chip integrated

microprocessor and peripheral combination that can be used in a variety of controller applications. It

particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a

next-generation MC68302 with higher performance in all areas of device operation, increased flexibility,

major extensions in capability, and higher integration. The term "quad" comes from the fact that there are

four serial communications controllers (SCCs) on the device; however, there are actually seven serial

channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

QUICC Key Features

The following list summarizes the key MC68360 QUICC features:

• CPU32+ Processor (4.5 MIPS at 25 MHz)

— 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)

— Background Debug Mode

— Byte-Misaligned Addressing

• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)

• Up to 32 Address Lines (At Least 28 Always Available)

• Complete Static Design (0–25-MHz Operation)

• Slave Mode To Disable CPU32+ (Allows Use with External Processors)

— Multiple QUICCs Can Share One System Bus (One Master)

— MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

fetch two word-length instructions in one bus cycle, filling the internal instruction queue more quickly. The

CPU32+ core can also read and write 32-bits of data in one bus cycle.

Although the CPU32+ instruction timings are improved, its instruction set is identical to that of the CPU32. It

will also execute the entire M68000 instruction set. It contains the same background debug mode (BDM)

features as the CPU32. No new compilers, assemblers, or other software support tools need be

implemented for the CPU32+; standard CPU32 tools can be used.

The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted) assumption that

a 10-MHz M68000 delivers 1 VAX MIPS. If an application requires more performance, the CPU32+ can be

disabled, allowing the rest of the QUICC to operate as an intelligent peripheral to a faster processor. The

QUICC provides a special mode called MC68040 companion mode to allow it to conveniently interface to

members of the M68040 family. This two-chip solution provides a 22-MIPS performance at 25 MHz.

The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32. These

features allow 16 or 32-bit data to be read or written at an odd address. The CPU32+ automatically performs

the number of bus cycles required.

Freescale Semiconductor, Inc...

System Integration Module (SIM60)

The SIM60 integrates general-purpose features that would be useful in almost any 32-bit processor system.

The term “SIM60” is derived from the QUICC part number, MC68360. The SIM60 is an enhanced version of

the SIM40 that exists on the MC68340 and MC68330 devices.

First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40

was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third, new configurations, such

as slave mode and internal accesses by an external master, are supported.

Although the QUICC is always a 32-bit device internally, it may be configured to operate with a 16-bit data

bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-,

16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode and 8- and 16-bit peripherals

and memory to exist in the 16-bit system bus mode.

Communications Processor Module (CPM)

The CPM contains features that allow the QUICC to excel in communications and control applications. These

features may be divided into three sub-groups:

• Communications Processor (CP)

• Two IDMA Controllers

For More Information On This Product,

Go to: www.freescale.com

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