KMPC8241TZQ166D datasheet, PDF

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KMPC8241TZQ166D: DescriptionIC mpu 32bit 166mhz 357-pbga; Categorysemiconductor The embedded processor and controller; File Size804KB，58 Pages; ManufacturerFREESCALE (NXP)

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IC mpu 32bit 166mhz 357-pbga

KMPC8241TZQ166D Parametric

Parameter Name	Attribute value
Datasheets
MPC8241
MPC8241TxxYYYx Hardware Spec
MPC8241 Fact Shee
Product Photos
MPC860 SERIES
Standard Package	2
Category	Integrated Circuits (ICs)
Family	Embedded - Microprocessors
Packaging	Tray
Core Process	PowerPC 603e
Number of Cores/Bus Width	1 Core, 32-Bi
Speed	166MHz
Co-Processors/DSP	-
RAM Controllers	SDRAM
Graphics Accelerati	N
Display & Interface Controllers	-
Etherne	-
SATA	-
USB	-
Voltage - I/O	3.3V
Operating Temperature	-40°C ~ 105°C
Security Features	-
Package / Case	357-BBGA
Supplier Device Package	357-PBGA (25x25)
Additional Interfaces	I²C, I²O, PCI, UART

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Freescale Semiconductor

Technical Data

Document Number: MPC8241EC

Rev. 10, 02/2009

MPC8241 Integrated Processor

Hardware Specifications

The MPC8241 combines a PowerPC™ MPC603E core with

a PCI bridge so that system designers can rapidly design

systems using peripherals designed for PCI and other

standard interfaces. Also, a high-performance memory

controller supports various types of ROM and SDRAM. The

MPC8241 is the second of a family of products that provide

system-level support for industry-standard interfaces with an

MPC603e processor core.

This hardware specification describes pertinent electrical

and physical characteristics of the MPC8241, which is based

on the MPC8245 design. For functional characteristics of the

processor, refer to the

MPC8245 Integrated Processor

Reference Manual

(MPC8245UM).

For published errata or updates to this document, visit the

web site listed on the back cover of the document.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical and Thermal Characteristics . . . . . . . . . . . . 6

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31

PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 39

System Design Information . . . . . . . . . . . . . . . . . . . 42

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 52

Document Revision History . . . . . . . . . . . . . . . . . . . 54

Overview

The MPC8241 integrated processor is composed of a

peripheral logic block and a 32-bit superscalar MPC603e

core, as shown in

Figure 1.

Features

The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),

memory controller, DMA controller, PIC interrupt controller, a message unit (and I

O interface), and an

C controller. The processor core is a full-featured, high-performance processor with floating-point

support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management

features. The integration reduces the overall packaging requirements and the number of discrete devices

required for an embedded system.

An internal peripheral logic bus interfaces the processor core to the peripheral logic. The core can operate

at a variety of frequencies, allowing the designer to trade performance for power consumption. The

processor core is clocked from a separate PLL that is referenced to the peripheral logic PLL, allowing the

microprocessor and the peripheral logic block to operate at different frequencies while maintaining a

synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus

width) and a 32-bit address bus along with control signals that enable the interface between the processor

and peripheral logic to be optimized for performance. PCI accesses to the MPC8241 memory space are

passed to the processor bus for snooping when snoop mode is enabled.

The general-purpose processor core and peripheral logic serve a variety of embedded applications. The

MPC8241 can be used as either a PCI host or PCI agent controller.

Features

Major features of the MPC8241 are as follows:

• Processor core

— High-performance, superscalar processor core

— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit

(LSU), system register unit (SRU), and a branch processing unit (BPU)

— 16-Kbyte instruction cache

— 16-Kbyte data cache

— Lockable L1 caches—entire cache or on a per-way basis up to three of four ways

— Dynamic power management—supports 60x nap, doze, and sleep modes

• Peripheral logic

— Peripheral logic bus

– Various operating frequencies and bus divider ratios

– 32-bit address bus, 64-bit data bus

– Full memory coherency

– Decoupled address and data buses for pipelining of peripheral logic bus accesses

– Store gathering on peripheral logic bus-to-PCI writes

— Memory interface

– Up to 2 Gbytes of SDRAM memory

– High-bandwidth data bus (32- or 64-bit) to SDRAM

– Programmable timing for SDRAM

– One to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices

MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

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