KMPC8540PX833LB datasheet, PDF

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KMPC8540PX833LB: DescriptionIC mpu pwrquicc 783-fcpbga; Categorysemiconductor The embedded processor and controller; File Size146KB，24 Pages; ManufacturerFREESCALE (NXP)

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IC mpu pwrquicc 783-fcpbga

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Parameter Name	Attribute value
Datasheets
MPC8540 Product Brief
MPC8540
Product Photos
784-BBGA, FCBGA
Standard Package	2
Category	Integrated Circuits (ICs)
Family	Embedded - Microprocessors
Packaging	Tray
Core Process	PowerPC e500
Number of Cores/Bus Width	1 Core, 32-Bi
Speed	833MHz
Co-Processors/DSP	-
RAM Controllers	DDR, SDRAM
Graphics Accelerati	N
Display & Interface Controllers	-
Etherne	10/100 Mbps (1), 10/100/1000 Mbps (2)
SATA	-
USB	-
Voltage - I/O	2.5V, 3.3V
Operating Temperature	0°C ~ 105°C
Security Features	-
Package / Case	784-BBGA, FCBGA
Supplier Device Package	783-FCPBGA (29x29)
Additional Interfaces	DUART, I²C, PCI, RapidIO

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Freescale Semiconductor

MPC8540PB

Rev. 0.1, 1/2005

MPC8540 PowerQUICC III™ Integrated Host

Processor Product Brief

The MPC8540 integrates a PowerPC™ processor core with system logic required for networking, storage, and

general-purpose embedded applications. The MPC8540 is a member of a growing family of products that combine

system-level support for industry standard interfaces to processors that implement the PowerPC architecture. This

chapter provides a high-level description of the features and functionality of the MPC8540 integrated

microprocessor.

Introduction

The MPC8540 uses the e500 core and RapidIO interconnect technology to balance processor performance with I/O

system throughput. The e500 core implements the enhanced Book E instruction set architecture and provides

unprecedented levels of hardware and software debugging support.

In addition, the MPC8540 offers 256 Kbytes of L2 cache, 2 integrated 10/100/1Gb three-speed Ethernet controllers

(TSECs), a 10/100 maintenance port, a DDR SDRAM memory controller, a 64-bit PCI/PCI-X controller, an 8-bit

RapidIO port, a programmable interrupt controller, an I

C controller, a 4-channel DMA controller, a

general-purpose I/O port, and 2 universal asynchronous receiver/transmitters (DUART). The high level of

integration in the MPC8540 simplifies board design and offers significant bandwidth and performance.

MPC8540 Overview

The following section provides a high-level overview of the features of the MPC8540.

MPC8540 Overview

•

Section 3.1, “e500 Core Overview,” in the reference manual includes a comprehensive list of e500 core

features.

256-Kbyte L2 cache/SRAM

— Can be configured as follows:

– Full cache mode (256-Kbyte cache)

– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two

128-Kbyte blocks)

– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM)

— Full error checking and correction (ECC) support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both

— External masters can force data to be allocated into the cache through programmed memory ranges or

special transaction types (stashing).

— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)

— Supports locking the entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately

— Read and write buffering for internal bus accesses

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transactions accesses for smaller than

cache-line accesses

Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 32-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

– Three inbound windows plus a configuration window on PCI/PCI-X

– Four inbound windows plus a default and configuration window on RapidIO

– Four outbound windows plus default translation for PCI

– Eight outbound windows plus default translation for RapidIO

DDR memory controller

— Programmable timing supporting DDR-1 SDRAM

— 64-bit data interface, up to 333-MHz data rate

— Four banks of memory supported, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full ECC support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions

— Sleep mode support for self-refresh SDRAM

MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1

Freescale Semiconductor

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