MPC603RRX266TC datasheet, PDF - EEWORLD Datasheet

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MPC603RRX266TC: DescriptionIC mpu 32bit 266mhz 255-cbga; Categorysemiconductor The embedded processor and controller; File Size472KB，31 Pages; ManufacturerFREESCALE (NXP)

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IC mpu 32bit 266mhz 255-cbga

MPC603RRX266TC Parametric

Parameter Name	Attribute value
Datasheets
MPC603E,R
MPC603
Product Photos
MPC603RRX300LC
Standard Package	60
Category	Integrated Circuits (ICs)
Family	Embedded - Microprocessors
Packaging	Tray
Core Process	PowerPC 603e
Number of Cores/Bus Width	1 Core, 32-Bi
Speed	266MHz
Co-Processors/DSP	-
RAM Controllers	-
Graphics Accelerati	N
Display & Interface Controllers	-
Etherne	-
SATA	-
USB	-
Voltage - I/O	3.3V
Operating Temperature	-40°C ~ 105°C
Security Features	-
Package / Case	255-BCBGA Exposed Pad
Supplier Device Package	255-FCCBGA (21x21)
Additional Interfaces	-

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Freescale Semiconductor

Technical Data

Document Number: MPC603E7TEC

Rev. 5, 09/2011

PowerPC 603e RISC Microprocessor Family:

PID7t-603e Hardware Specifications

The PowerPC™ 603e microprocessor is an implementation

of the PowerPC family of reduced instruction set computing

(RISC) microprocessors. In this document, the term ‘603e’

is used as an abbreviation for the PowerPC 603e

microprocessor. The PowerPC 603e microprocessors are

available from Freescale as MPC603e.

The 603e is implemented in several semiconductor

fabrication processes. Different processes may require

different supply voltages and may have other electrical

differences but will have the same functionality. As a

technical designator to distinguish between 603e

implementations in various processes, a prefix composed of

the processor version register (PVR) value and a process

identifier (PID) is assigned to the various implementations as

shown in

Table 1.

This document describes the pertinent physical

characteristics of the PID7t-603e from Freescale. For

functional characteristics of the 603e, refer to the

PowerPC

603e RISC Microprocessor User’s Manual.

To locate any published errata or updates for this document,

refer to the website at www.freescale.com.

10.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Electrical and Thermal Characteristics . . . . . . . . . . . . 4

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 17

System Design Information . . . . . . . . . . . . . . . . . . . . 20

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Overview

Table 1. PowerPC 603e Microprocessors from Freescale

Technical

Designator

PID6-603e

PID7v-603e

PID7t-603e

Process

0.5 µm CMOS, 4LM

0.35 µm CMOS, 5LM

0.29 µm CMOS, 5LM

Core Voltage I/O Voltage

5-Volt

(V)

Tolerant

3.3

2.5

3.3

Yes

Part Number

MPC603E

XPC603P (end-of-life)

MPC603R

Overview

The 603e is a low-power implementation of the PowerPC microprocessor family of RISC

microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture specification that

provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types

of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer

data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor. The

fourth is a dynamic power management mode that causes the functional units in the 603e to automatically

enter a low-power mode when the functional units are idle without affecting operational performance,

software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.

Instructions can execute out of order for increased performance; however, the 603e makes completion

appear sequential.

The 603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch

processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute

five instructions in parallel and the use of simple instructions with rapid execution times yield high

efficiency and throughput for 603e-based systems. Most integer instructions execute in one clock cycle.

The FPU is pipelined, so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches

for instructions and data and on-chip instruction and data memory management units (MMUs). The

MMUs contain 64-entry, two-way, set-associative data and instruction translation lookaside buffers

(DTLB and ITLB) that provide support for demand-paged virtual memory address translation and

variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement

algorithm. The 603e also supports block address translation through the use of two independent instruction

and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are

compared simultaneously with all four entries in the BAT array during block translation. In accordance

with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT

translation takes priority.

The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol

allows multiple masters to compete for system resources through a central external arbiter. The 603e

provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states.

This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol

PID7t-603e Hardware Specifications, Rev. 5

Freescale Semiconductor

Features

and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst

data transfers for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface

compatibility with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The

CBGA package supports speed bins of 200, 266, and 300 MHz. The PBGA package is a pin-compatible

drop in replacement for the CBGA; however, this package only supports speeds up to 200 MHz.

Features

This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major

features of the 603e are as follows:

• High-performance, superscalar microprocessor

— As many as three instructions issued and retired per clock

— As many as five instructions in execution per clock

— Single-cycle execution for most instructions

— Pipelined FPU for all single-precision and most double-precision operations

• Five independent execution units and two register files

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754-compliant FPU for both single- and double-precision operations

— LSU for data transfer between data cache and GPRs and FPRs

— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and

integer add/compare instructions

— 32 GPRs for integer operands

— 32 FPRs for single- or double-precision operands

• High instruction and data throughput

— Zero-cycle branch capability (branch folding)

— Programmable static branch prediction on unresolved conditional branches

— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

— A six-entry instruction queue that provides lookahead capability

— Independent pipelines with feed-forwarding that reduces data dependencies in hardware

— 16-Kbyte data cache—four-way, set-associative physically addressed; LRU replacement

algorithm

— 16-Kbyte instruction cache—four-way, set-associative physically addressed; LRU

replacement algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

— BPU that performs CR lookahead operations

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

PID7t-603e Hardware Specifications, Rev. 5

Freescale Semiconductor

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