™
Le7942B
A
Voice Solution
Subscriber Line Interface Circuit
VE580 Series
Compatible with Le7942 Device
Tip Open state for ground-start lines
–19 V to –58 V battery operation
Ideal for PBX and KTS applications
On-chip switching regulator for low-power
dissipation
Can be used with or without the on-chip switching
regulator
On-hook transmission
DISTINCTIVE CHARACTERISTICS
Programmable constant-current feed
Receive current gain = 500
Programmable loop-detect threshold
Low standby power
Performs polarity reversal
Ground-key detector
Pin for external ground-key noise filter capacitor
Test relay driver option
BLOCK DIAGRAM
Test Relay Driver
Ring Relay Driver
TESTOUT
RINGOUT
C1
C2
HPA
Two-Wire
Interface
HPB
Signal
Transmission
Off-Hook
Detector
RD
Power-Feed
Controller
DA
DB
VREG
L
VBAT
BGND
CHS QBAT CHCLK
VCC
VEE AGND/DGND
15474A-001
A(TIP)
Ground-Key
Detector
Input Decoder
and Control
C3
C4
E1
DET
GKFIL
RSN
VTX
B(RING)
RDC
CAS
Ring-Trip
Detector
Switching
Regulator
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and
technology of Legerity Holdings.
Document ID#
081195
Date:
Rev:
E
Version:
Distribution:
Public Document
Sep 19, 2007
2
Le7942B
ORDERING INFORMATION
Standard Products
Data Sheet
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Le7942B
J
C
C = Commercial (0°C to 70°C)*
PLCC package
PACKAGING MATERIAL
Blank= Standard package
D= Green package (see note)
DEVICE NUMBER/DESCRIPTION
Le7942B
Subscriber Line Interface Circuit
PERFORMANCE GRADE
Blank = Standard specification
–1 = Performance Grading
–2 = Performance Grading
Note:
The green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
Valid Combinations
Valid Combinations
Green Package
Le7942BDJC
Le7942B–1DJC
Le7942B–2DJC
Non-Green Package
Le7942BJC
Le7942B-1JC
Le7942B-2JC
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local Legerity sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and to
obtain additional data on Legerity’s standard
military–grade products.
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Zarlink Semiconductor Inc.
Le7942B
CONNECTION DIAGRAMS
Top View
RINGOUT
Data Sheet
B(RING)
VREG
BGND
VCC
A(TIP)
31
4
TP
TESTOUT
L
VBAT
QBAT
CHS
CHCLK
C4
E1
5
6
7
8
9
10
11
12
13
14
DET
3
2
1
32
DB
30
29
28
27
TP
DA
RD
HPB
HPA
VTX
VBREF
RSN
AGND/DGND
26
25
24
23
22
21
GKFIL
32-Pin PLCC
15
C2
16
C3
17 18
C1
CAS
19 20
RDC
Notes:
1. Pin 1 is marked for orientation.
2. TP is a thermal conduction pin tied to substrate (QBAT).
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Zarlink Semiconductor Inc.
Le7942B
PIN DESCRIPTIONS
Pin Names
AGND/DGND
A (TIP)
BGND
B (RING)
C3–C1
C4
CAS
CHCLK
CHS
DA
DB
DET
Type
Gnd
Output
Gnd
Output
Input
Input
Capacitor
Input
Input
Input
Input
Output
Analog and Digital ground.
Output of A(TIP) power amplifier.
Battery (power) ground.
Output of B(RING) power amplifier.
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
Test Relay Driver Command. TTL compatible. A logic Low enables the driver.
Description
Data Sheet
Anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation
region.
Chopper Clock. Input to switching regulator (TTL compatible). Freq = 256 kHz (typ).
(See Note 1).
Chopper Stabilization. (See Note 1) Connection for external chopper stabilizing components.
Ring-trip negative. Negative input to ring-trip comparator.
Ring-trip positive. Positive input to ring-trip comparator.
Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The
detector is selected by the logic inputs (C3–C1, E1). The output is open-collector with a built-in
15 kΩ pull-up resistor.
Ground-Key Enable. E1 = High connects the ground-key detector to DET. E1 = Low connects the
off-hook or ring-trip detector to DET.
Connection for external ground-key, noise-filter capacitor. (See Note 2.)
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
Switching Regulator Power Transistor. Connection point for filter inductor and anode of Switching
Regulator Power Transistor. Connection point for filter inductor and anode of catch diode. Has up
to 60 V of pulse waveform on it and must be isolated from sensitive circuits. Keep the diode
connections short because of the high currents and high di/dt.
Quiet Battery. (See Note 1). Filtered battery supply for the signal processing circuits.
Detector resistor. Detector threshold set and filter pin. May be connected to ground or -5V.
DC feed resistor. Connection point for the DC feed current programming network. The other end
of the network connects to the receiver summing node (RSN).
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
(See Note 3)
Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal
to 500 x the current into this pin. The networks that program receive gain, two-wire impedance,
and feed current all connect to this node.
Test Relay Driver. Open collector driver with emitter internally connected to BGND.
(See Note 3)
Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as
open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper
on the board to enhance heat dissipation.
Battery supply.
+5 V power supply.
Reference voltage. No current on the pin. May be connected to QBAT or –5 V.
Regulated Voltage. (See Note 1.) Provides negative power supply for power amplifiers.
Connection point for inductor, filter capacitor, and chopper stabilization.
Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage.
VTX also sources the two-wire input impedance programming network.
E1
GKFIL
HPA
HPB
L
Input
—
Capacitor
Capacitor
Output
(See Note 1)
QBAT
RD
RDC
RINGOUT
RSN
Battery
Resistor
Resistor
Output
Input
TESTOUT
TP
Output
Thermal
VBAT
VCC
VBREF
VREG
VTX
Battery
Power
Power
Input
Output
Notes:
1. All pins, except CHCLK, connect to VBAT when using SLIC without a switching regulator. CHCLK is connected to AGND/
DGND.
2. To prevent noise pickup by the detection circuits when using Ground-Key Detect state (E1 = logical 1), a 3300 pF minimum
bypass capacitor is recommended between the GKFIL pin and ground.
3. Each relay driver has a zener clamp to BGND.
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Zarlink Semiconductor Inc.
Le7942B
ABSOLUTE MAXIMUM RATINGS
Storage temperature . . . . . . . . . . . . –55°C to +150°C
V
CC
with respect to AGND/DGND . . . –0.4 V to +7.0 V
V
EE
with respect to AGND/DGND . . . +0.4 V to QBAT
V
BAT
with respect to AGND/DGND. . . +0.4 V to –70 V
Note:
Rise time of V
BAT
(dv/dt) must be limited to 27 V/µs or
less when Q
BAT
bypass = 0.33
µF.
Data Sheet
OPERATING RANGES
Commercial (C) Devices
Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C*
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to QBAT
V
BAT
. . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –58 V**
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to
AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV
Load Resistance on VTX to ground . . . . . . 10 kΩ min
The Operating Ranges define those limits between which the
functionality of the device is guaranteed.
*Legerity guarantees the performance of this device over
commercial (0 to 70°C) and industrial (-40 to 85
°C)
temperature ranges by conducting electrical characterization
over each range and by conducting a production test with
single insertion coupled to periodic sampling. These
characterization and test procedures comply with section
4.6.2 of Bellcore TR-TSY-000357 Component Reliability
Assurance Requireme nts for Telecommu nications
Equipment.
BGND with respect to AGND/DGND . +1.0 V to –3.0 V
A(TIP) or B(RING) to BGND:
Continuous . . . . . . . . . . . . . . . . . . –70 V to +1.0 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . . –70 V to +5.0 V
1
µs
(f = 0.1 Hz) . . . . . . . . . . . . . . . –90 V to +10 V
250 ns (f = 0.1 Hz) . . . . . . . . . . . . –120 V to +15 V
Current from A(TIP) or B(RING).
. . . . . . . . . . .±150
mA
Voltage on RINGOUT, TESTOUT . . . . BGND to + 7 V
Voltage on RINGOUT, TESTOUT (transient)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGND to +10 V
Current through relay drivers . . . . . . . . . . . . . . 60 mA
Voltage on ring-trip inputs
(DA and DB) . . . . . . . . . . . . . . . . . . . . . V
BAT
to 0 V
Current into ring-trip inputs
. . . . . . . . . . . . . . . . .±10
mA
Peak current into regulator
switch (L pin). . . . . . . . . . . . . . . . . . . . . . . 150 mA
Switcher transient peak off
voltage on L pin. . . . . . . . . . . . . . . . . . . . . . +1.0 V
C4–C1, E1, CHCLK to
AGND/DGND . . . . . . . . . . . .–0.4 V to V
CC
+ 0.4 V
Maximum power dissipation, T
A
(see note) . . . . .70°C
In 32-pin PLCC package. . . . . . . . . . . . . . . 1.74 W
Note:
Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165°C. The device
should never be exposed to this temperature. Operation
above 145°C junction temperature may degrade device
reliability. See the SLIC Packaging Considerations for more
information.
Stresses above those listed under Absolute Maximum Ratings
cancause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
**
Can be used without switching regulator components in this
range of battery voltages, provided maximum power
dissipation specifications are not exceeded.
Package Assembly
The non-green package devices are assembled with
industry-standard mold compounds, and the leads
possess a tin/lead (Sn/Pb) plating. These packages
are compatible with conventional SnPb eutectic solder
board assembly processes. The peak soldering
temperature should not exceed 225°C during printed
circuit board assembly.
The green package devices are assembled with
enhanced environmental compatible lead-free,
halogen-free, and antimony-free materials. The leads
possess a matte-tin plating which is compatible with
conventional board assembly processes or newer
lead-free board assembly processes. The peak
soldering temperature should not exceed 245°C during
printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the
recommended solder reflow temperature profile
5
Zarlink Semiconductor Inc.
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