FSTU6800 10-Bit Bus Switch with Precharged Outputs
December 1998
Revised October 2006
FSTU6800
10-Bit Bus Switch with Precharged Outputs
and
−
2V Undershoot Protection
General Description
The Fairchild Switch FSTU6800 provides 10-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. Both the A Ports and the B
Ports have “undershoot hardened” circuit protection to sup-
port an extended input range to 2.0V below ground. Fair-
child’s integrated Undershoot Hardened Circuit (UHC®)
senses undershoot at the I/Os, and responds by preventing
voltage differentials from developing and turning on the
switch. The device also precharges the B Port to a select-
able bias voltage (BiasV) to minimize live insertion noise.
The device is organized as a 10-bit switch with a bus
enable (OE) signal. When OE is LOW, the switch is ON
and Port A is connected to Port B. When OE is HIGH, the
switch is OPEN and the B Port is precharged to BiasV
through an equivalent 10-k
Ω
resistor.
Features
s
4
Ω
switch connection between two ports.
s
Undershoot Hardened to -2.0V.
s
Soft enable turn-on to minimize bus-to-bus charge
sharing during enable.
s
Low l
CC
.
s
Zero bounce in flow-through mode.
s
Output precharge to minimize live insertion noise.
s
Control inputs compatible with TTL level.
s
See Applications Note AN-5008 for details.
Ordering Code:
Order Number
FSTU6800WM
FSTU6800QSC
FSTU6800MTC
Package Number
M24B
MQA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Name
OE
A
B
BiasV
Description
Bus Switch Enable
Bus A
Bus B
Bus B Voltage Bias
Truth Table
OE
L
H
B
0
–B
9
A
0
–A
9
BiasV
Function
Connect
Precharge
UHC® is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS500194
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FSTU6800
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
)
Bias V Voltage Range
DC Input Voltage (V
IN
) (Note 2)
DC Input Diode Current (l
IK
) V
IN
<
0V
DC Output (I
OUT
) Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
−
0.5V to
+
7.0V
−
2.0V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50mA
128mA
Recommended Operating
Conditions
(Note 3)
Power Supply Operating (V
CC
)
Precharge Supply (BiasV)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0 nS/V to 5 nS/V
0nS/V to DC
4.0V to 5.5V
1.5V to V
CC
0V to 5.5V
0V to 5.5V
+
/
−
100mA
−
65
°
C to
+
150
°
C
−
40
°
C to
+
85
°
C
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions tables will define the conditions
for actual device operation.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
4.5
4.0–5.5
4.0–5.5
5.5
4.5
5.5
4.5
4.5
4.5
4.0
I
CC
∆
I
CC
Quiescent Supply Current
Increase in I
CC
per Input
5.5
5.5
4
4
8
11
0.25
±1.0
7
7
15
20
3
2.5
2.0
0.8
±1.0
T
A
= −40 °C
to
+85 °C
Min
Typ
(Note 5)
Max
−1.2
Units
Conditions
V
IK
V
IH
V
IL
I
I
I
O
I
OZ
R
ON
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
Output Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 4)
V
V
V
µA
mA
µA
Ω
Ω
Ω
Ω
µA
mA
I
IN
= −18mA
0
≤
V
IN
≤
5.5V
BiasV
=
2.4V, B
=
0
0
≤
A
≤
V
CC
, V
IN
=
V
IH
V
S
=
0V, I
IN
=
64 mA
V
S
=
0V, I
IN
=
30 mA
V
S
=
2.4V, I
IN
=
15 mA
V
S
=
2.4V, I
IN
=
15 mA
V
S
=
V
CC
or GND, I
OUT
=
0
OE input at 3.4V
Other inputs at V
CC
or GND
I
BIAS
I
OZU
V
IKU
Bias Pin Leakage Current
Switch Undershoot Current
Voltage Undershoot
5.5
5.5
5.5
±1.0
100
−2.0
µA
µA
V
OE
=
0V, B
=
0V, BiasV
=
5.5V
I
IN
= −20
mA, OE
=
5.5V, V
OUT
≥
V
IH
0.0 mA
≥
I
IN
≥ −50
mA, OE
=
5.5V
Note 4:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5:
Typical values are at V
CC
=
5.0V and T
A
= +25°C
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2
FSTU6800
AC Electrical Characteristics
T
A
= −40 °C
to
+85 °C,
C
L
=
50 pF, RU
=
RD
=
500Ω
Symbol
Parameter
V
CC
=
4.5 – 5.5V
Min
t
PHL
,t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Prop Delay Bus to Bus (Note 6)
Output Enable Time
7.0
7.0
1.0
1.0
Max
0.25
30.0
30.0
6.1
7.3
V
CC
=
4.0V
Min
Max
0.25
35.0
35.0
6.5
6.8
ns
ns
ns
ns
ns
V
I
=
OPEN
V
I
=
OPEN
BiasV
=
GND
V
I
=
7V
BiasV
=
3V
V
I
=
OPEN
BiasV
=
GND
V
I
=
7V
BiasV
=
3V
Figures 1, 2
Units
Conditions
Figure No.
Figures 1, 2
Figures 1, 2
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance
Symbol
C
IN
C
I/O
(Note 7)
Parameter
Typ
3
5
Max
Units
pF
pF
Conditions
V
CC
=
5.0V
V
CC
, OE
=
5.0V
Control Pin Input Capacitance
Input/Output Capacitance
Note 7:
T
A
= +25°C,
f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50
Ω
source terminated in 50
Ω,
RU
=
RD
=
500
Ω
Note:
C
L
includes load and stray capacitance, C
L
=
50 pF
Note:
Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FSTU6800
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA24
www.fairchildsemi.com
4
FSTU6800 10-Bit Bus Switch with Precharged Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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