™
Le79489
Subscriber Line Interface Circuit
Ve580 Series
DISTINCTIVE CHARACTERISTICS
Ideal for low power sensitive applications
Low standby power (normal and reverse)
Automatic on-chip battery switching
On-chip thermal management
On-chip thermal shutdown
–20 V to –60 V battery operation
Programmable current limit
Programmable resistive feed
Programmable loop-detect threshold
Selectable overhead for metering applications
Two-wire impedance set by single external impedance
On-chip ring and test relay drivers and relay snubber
circuits
Polarity reversal (full transmission)
Loop and ground-key detector
Comparator for ring-trip detection
Ground-start capability
On-hook transmission
BLOCK DIAGRAM
TMG
DA
DB
Test Relay
Driver
Ring Relay
Driver
Ring-Trip
Comparator
Two-Wire
Interface
Ground-Key
Detector
Loop Detector
Signal
Transmission
Power-Feed
Controller
Switch Control
TESTOUT
RINGOUT
A(TIP)
C1
HPA
Input
Decoder
and
Control
C2
C3
C4
E1
HPB
DET
RD
VTX
RSN
RDC
CAS
OVH
RFA
B(RING)
VBAT2
VBAT1
BGND
BSWOUT BSWEN BSWTH
VCC
AGND/DGND
Document ID#
080201
Date:
Sep 19, 2007
Rev:
G
Version:
3
Distribution:
Public Document
Le79489
ORDERING INFORMATION
Standard Products
Data Sheet
Zarlink
standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a com-
bination of the elements below.
Le79489*
D
J
C
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-pin Plastic Leaded Chip Carrier (PL 032)
PACKAGING
D = Green package
PERFORMANCE GRADE OPTION
Blank = No performance grade option
–2 = 60 dB Longitudinal Balance, Polarity Reversal
–3 = 52 dB Longitudinal Balance, No Polarity Reversal
DEVICE NUMBER/DESCRIPTION
Le79489
Subscriber Line Interface Circuit
Valid Combinations
Le79489*
(Blank)
–2
–3
DJC
1, 2
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Contact
Zarlink
sales to confirm availability of specific valid
combinations and to obtain additional data on
Zarlink’s
standard military–grade products.
1. For delivery using a tape and reel packing system, add a "T"
suffix to the OPN (Ordering Part Number) when placing an
order.
2. The green package meets RoHS Directive 2002/95/EC of
the European Council to minimize the environmental impact
of electrical equipment.
*Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix, until such time as
all inventory bearing this mark has been depleted. It should be noted that parts marked with either the "Am" or the "Le" part number
prefix are equivalent devices in terms of form, fit, and function. The only difference between the two is in the part number prefix appearing
on the topside mark.
2
Zarlink Semiconductor Inc.
Le79489
CONNECTION DIAGRAMS
Top View
RINGOUT
B(RING)
VBAT2
A(TIP)
BGND
Data Sheet
VCC
4
TESTOUT
BSWOUT
TMG
VBAT1
C4
BSWEN
C1
E1
DET
5
6
7
8
9
10
11
12
13
14
C3
3
2
1
32
31 30
29
28
27
26
DA
RD
HPB
HPA
NC
VTX
RSVD
RSN
AGND/DGND
32-Pin PLCC
DB
25
24
23
22
21
20
RDC
15
C2
16
BSWTH
17
CAS
18
OVH
19
RFA
Notes:
1. Pin 1 is marked for orientation.
2. NC = No Connect
3. RSVD = Reserved. Do not connect to this pin.
3
Zarlink Semiconductor Inc.
Le79489
PIN DESCRIPTIONS
Pin Names
AGND/DGND
A(TIP)
BGND
B(RING)
BSWEN
Type
Gnd
Output
Gnd
Output
—
Analog and Digital ground.
Output of A(TIP) power amplifier.
Battery (power) ground.
Output of B(RING) power amplifier.
Description
Data Sheet
Battery Switch Control. Internally connected to automatic battery switch circuitry. BSWEN can be
overridden by external logic. BSWEN Low connects VBAT1 to VBAT2. BSWEN High disconnects
VBAT1 from VBAT2.
Buffered Output. Internally connected to battery switch circuitry. The output is open-collector with a
built-in pull-up resistor. BSWOUT Low indicates VBAT1 is connected to VBAT2. BSWOUT High
indicates VBAT1 is disconnected from VBAT2. This output is valid only in the Active states.
Input for setting automatic battery switch threshold. Normally tied to Battery 2. Tie to ground for
manual switching.
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
Test Relay Input – Active Low. 1 = Off. 0 = On.
Anti-sat pin for capacitor to filter reference voltage when operating in anti-sat region.
Ring-trip negative. Negative input to ring-trip comparator.
Ring-trip positive. Positive input to ring-trip comparator.
Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The detector
is selected by the logic inputs (C3–C1). The output is open-collector with a built-in 15 kΩ pull-up
resistor.
Ground-Key Detect Select. E1 = 1 selects the hook switch detector. E1 = 0 selects the ground-key
detector. In the Tip Open state, ground key is selected independent of E1.
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
No connect. This pin not internally connected.
Overhead Control. Logic High enables minimized nonmetering overhead. Logic Low enables 2.2 V
metering DC overhead. TTL-compatible.
Detector resistor. Detector threshold set and filter pin.
DC feed resistor. Connection point for the DC feed current programming network. The other end of the
network connects to the receiver summing node (RSN). Connection point for the DC feed current
programming network. The other end of the network connects to RSN. V
RDC
is negative for normal
polarity and positive for reverse polarity.
Resistive feed adjust. Adjust the DC feed resistance gain coefficient, GDC, with external resistor
connected to ground.
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal to
500 times the current into this pin. The networks that program receive gain, two-wire impedance, and
feed current all connect to this node.
Reserved. These pins are reserved for
Zarlink
use. Make no connection to these pins.
Test Relay Driver. Open collector driver with emitter internally connected to AGND.
Thermal Management. External resistor connects this pin to VBAT2 to offload power dissipation from
SLIC. Functions during normal polarity, Active state.
Most negative battery supply and substrate connection.
Battery supply for output power amplifiers. Switched to VBAT1 by BSWEN.
+5 V power supply.
Transmit Audio. This output is a 0.5066 unity gain version of the A(TIP) and B(RING) metallic voltage.
VTX also sources the two-wire input impedance programming network.
This must be electrically tied to VBAT1.
BSWOUT
Output
BSWTH
C3–C1
C4
CAS
DA
DB
DET
Input
Input
Input
Capacitor
Input
Input
Output
E1
HPA
HPB
NC
OVH
RD
RDC
Input
Capacitor
Capacitor
—
Input
Resistor
Resistor
RFA
RINGOUT
RSN
—
Output
Input
RSVD
TESTOUT
TMG
VBAT1
VBAT2
VCC
VTX
Exposed Pad
—
Output
—
Battery
Battery
Power
Output
Battery
4
Zarlink Semiconductor Inc.
Le79489
ABSOLUTE MAXIMUM RATINGS
Storage temperature. . . . . . . . . . . . . . . . . –55°C to +150°C
With respect to AGND/DGND:
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +7.0 V
V
BAT1
Continuous. . . . . . . . . . . . . . . . . . . . . . +0.4 V to –70 V
10 ms . . . . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V
V
BAT2
and BSWTH. . . . . . . . . . . . . . . . . . +0.4 V to V
BAT1
BGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3 V to –3 V
A(TIP) or B(RING) with respect to BGND:
Continuous. . . . . . . . . . . . . . . . . . . . . . . .V
BAT1
to +1 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . . . . –70 V to +5 V
1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . . . . . –80 V to +8 V
250 ns (f = 0.1 Hz). . . . . . . . . . . . . . . . . –90 V to +12 V
Current from A(TIP) or B(RING) . . . . . . . . . . . . . ±150 mA
TESTOUT/RINGOUT/current . . . . . . . . . . . . . . . . . 80 mA
TESTOUT/RINGOUT/voltage . . . . . . . . . . BGND to +7 V
TESTOUT/RINGOUT/transient . . . . . . . . BGND to +10 V
DA and DB inputs
Voltage on ring-trip inputs. . . . . . . . . . . . . V
BAT1
to 0 V
Current on ring-trip inputs. . . . . . . . . . . . . . . . . ±10 mA
C4–C1, BSWEN, OVH, E1
Input voltage . . . . . . . . . . . . . . . –0.4 V to V
CC
+ 0.4 V
Maximum power dissipation, continuous*
T
A
= 70°C, No heat sink (see note):
In 32-pin PLCC package . . . . . . . . . . . . . . . . . . . .1.7 W
Thermal data (θ
JA
)
In 32-pin PLCC package ..............................43°C/W typ
ESD immunity (HBM) . . . . . . JESD22 Class 1C compliant
* Thermal limiting circuitry on chip will shut down the circuit at a
junction temperature of about 165°C. Continuous operation above
145°C junction temperature may degrade device reliability.
Stresses above those listed under Absolute Maximum Ratings may
cause permanent device failure. Functionality at or above these lim-
its is not implied. Exposure to Absolute Maximum Ratings for ex-
tended periods may affect device reliability.
Data Sheet
OPERATING RANGES
Commercial (C) Devices
Ambient temperature . . . . . . . . . . . . . . . . –40°C to +85°C*
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
BAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40.5 V to –60 V
BAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 V to BAT1
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to GND . . . . . . .–100 mV to +100 mV
Load resistance on VTX to GND . . . . . . . . . . . .20 kΩ min
Operating ranges define those limits over which the functionality of
the device is guaranteed by production testing.
*Zarlink guarantees the performance of this device over
commercial (0 to 70°C) and industrial (-40 to 85
°C)
temperature
ranges by conducting electrical characterization over each range
and by conducting a production test with single insertion coupled
to periodic sampling. These characterization and test procedures
comply with section 4.6.2 of Bellcore TR-TSY-000357 Component
Reliability Assurance Requirements for Telecommunications
Equipment.
Package Assembly
Green package devices are assembled with enhanced,
environmental compatible lead-free, halogen-free, and
antimony-free materials. The leads possess a matte-tin
plating which is compatible with conventional board assembly
processes or newer lead-free board assembly processes.
The peak soldering temperature should not exceed 245°C
during printed circuit board
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Zarlink Semiconductor Inc.
京公网安备 11010802033920号
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