The NAU8812 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice telephony
related applications. Functions include Automatic Level Control (ALC) with noise gate, PGA, standard audio interface
I S, PCM with time slot assignment, and on-chip PLL. The device provides one differential microphone input and one
single ended auxiliary input (multi purpose). There are few variable gain control stages in the audio path. It also
includes MONO line output and integrated BTL speaker driver.
The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input
sources. The microphone amplifiers have a programmable gain from -12dB to +35.25dB to handle both amplified
microphones. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice band
digital filtering. Voice-band data is accepted by the audio interface (I S). The DAC converter path includes filtering
and mixing, programmable-gain amplifiers (PGA), and soft muting.
The digital interfaces, 2-Wire or SPI, have
2
2
independent supply voltage to allow integration into multiple supply systems. The NAU8812 operates at supply
voltages from 2.5V to 3.6V, although the digital core can operate at voltage as low as 1.71V to save power.
2.
FEATURES
Low Power, Low Voltage
Analog Supply: 2.5V to 3.6V
Digital Supply: 1.71V to 3.6V
Nominal Operating Voltage: 3.3V
Additional features
Programmable ALC
ADC Notch Filter
Programmable High Pass Filter
Digital A/D-D/A Passthrough
AEC-Q100 & TS16949 qualification
Industrial temperature: range: –40C to +85C
Applications
VoIP Telephones]
Conference speaker-phone
IP PBX
Mobile Telephone Hands-free Kits
Residential & Consumer Intercoms
24-bit signal processing linear Audio CODEC
Audio DAC: 93dB SNR and -84dB THD
Audio ADC: 91dB SNR and -79dB THD
Support variable sample rates from 8 - 48kHz
Integrated BTL Speaker Driver 800mW (8Ω / 5V)
Integrated Headset Driver 40mW (16Ω / 3.3V)
Analog I/O
Integrated programmable Microphone Amplifier
Integrated Line Input and Line Output
Earphone / Speaker / Line Output selection
Microphone / Line Inputs selection
Low Noise bias supplied for microphone
On-chip PLL
Interfaces
2
I S digital interface PCM time slot assignment
2
SPI & 2-Wire serial control Interface (I C style;
Read/Write capable)
Line Driver
AUX
Microphone
Interface
ADC Filter
Input
Mixers
&
Gain
Stage
AUX
DAC Filter
Output
Mixers
ADC
Volume
Control
HPF
MIC-
MIC+
Volume
Control
Limiter
DAC
&
Speaker
Volume
-1
BTL
Speaker
Driver
SPK+
SPK-
Notch Filter
PLL
MICBIAS
Micophone
Bias
GPIO
Digital Audio Interface
I
2
S
PCM
Serial Control Interface
2-wire
SPI
CSb/GPIO
Audio I/O
Digital I/O
emPowerAudio
™
Datasheet Revision 2.0
Page 1 of 109
January 2011
NAU8812
3.
PIN CONFIGURATION
VREF
MIC -
MIC +
MICBIAS
NC
VDDA
VSSA
VSSA
VDDC
VDDB
VSSD
ADCOUT
DACIN
FS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
AUX
VDDSPK
VDDSPK
SPKOUT -
VSSSPK
VSSSPK
SPKOUT +
MOUT
MODE
SDIO
SCLK
CSb/GPIO
MCLK
BCLK
NAU8812
MONO AUDIO
CODEC
SSOP 28-Pin
23
22
21
20
19
18
17
16
15
Figure 1: 28-Pin SSOP Package
MICBIAS
SPKOUT -
25
VDDSPK
27
VDDSPK
26
MIC +
MIC -
VREF
29
32
31
30
28
AUX
NC
VDDA
VSSA
VSSA
VDDL
VDDC
VDDB
VSSD
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
24
23
VSSSPK
VSSSPK
SPKOUT +
MOUT
NC
MODE
SO
SDIO
NAU8812
MONO AUDIO
CODEC
QFN 32-Pin
22
21
20
19
18
17
VSSD
DACIN
FS
BCLK
ADCOUT
MCLK
Figure 2: 32-Pin QFN Package
emPowerAudio
™
Datasheet Revision 2.0
Page 2 of 109
January 2011
CSb/GPIO
SCLK
NAU8812
4.
PIN DESCRIPTION
28-Pin
1
2
3
4
5
6
7
8
-
9
10
11
-
12
13
14
15
16
17
18
19
-
20
-
21
22
23
24
25
26
27
28
32-Pin
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Functionality
Decoupling internal analog mid supply reference
Microphone Negative Input
voltage
Microphone Positive Input
Microphone Bias
No Connect
Analog Supply
Analog Ground
Analog Ground
Logic supply voltage. This pin should not be
connected up to an external supply
Digital Supply Core
Digital Supply Buffer
Digital Ground
Digital Ground
Digital Audio Data Output
Digital Audio Data Input
Frame Sync
Bit Clock
Master Clock
SPI Chip Select or General Purposes 1 I/O
SPI or 2-Wire Serial Clock
SPI Data In or 2-Wire I/O
SPI Data Output
Interface Select (2-Wire or SPI)
No Connect
MONO Output
Speaker Positive Output
Speaker Ground
Speaker Ground
Speaker Negative Output
Speaker Supply
Speaker Supply
Auxiliary Input
A
A
A
A
A
A
A
A
O
O
O
O
O
I
I
I
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
I
O
O
O
I
I
O
O
O
I
I/O
I/O
I
I/O
I
O
O
I
A/D
A
A
A
A
Pin Type
O
I
I
O
Pin Name
VREF
MIC-
MIC+
MICBIAS
NC
VDDA
VSSA
VSSA
VDDL
VDDC
VDDB
VSSD
VSSD
ADCOUT
DACIN
FS
BCLK
MCLK
CSb/GPIO
SCLK
SDIO
SO
MODE
NC
MOUT
SPKOUT+
VSSSPK
VSSSPK
SPKOUT-
VDDSPK
VDDSPK
AUX
Table 1: Pin Description for SSOP and QFN Packages
Notes
1.
2.
3.
4.
The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground
should be thermally tied to the PCB, and electrically tied to the analog ground.
Unused analog input pins should be left as no-connection.
Under all condition when digital pins are not used they should be tied to ground.
Pins designated as NC (Not Internally Connected) should be left as no-connection
emPowerAudio
™
Datasheet Revision 2.0
Page 3 of 109
January 2011
5.
emPowerAudio
™
VSSA
VSSA
VSSSPK
VDDA
VSSSPK
VDDSPK
VDDSPK
VDDB
VSSD
VDDC
NC
Datasheet Revision 2.0
BLOCK DIAGRAM
AUXM[3]
(0x2C)
20k
20k
AUX
AUXMOUT[2]
(0x38)
AUXM[3]
(0x2C)
AUXEN[6]
(0x01)
AUX BYPASS
MOUTMXEN[3]
(0x03)
AUXBSTGAIN[2:0]
(0x2F)
BSTEN[4]
(0x02)
DACMOUT[0]
(0x38)
MOUT3V[3]
(0x31)
VREF
PGAEN[2]
(0x02)
AUXPGA[2]
(0x2C)
AUXBSTGAIN[2:0]
(0x2F) = 000
PGABST[8]
(0x2F)
Σ
HPF
BYPMOUT[1]
(0x38)
1.5X
1.0X
MOUT
-12 dB to
+35.25 dB
MIC-
PGAMT[6]
(0x2D)
PGAGAIN
(0x2D)
ADCEN[0]
(0x02)
DACEN[0]
(0x03)
PMICBSTGAIN[6:4]
(0x2F)
Figure 3: NAU8812 General Block Diagram
Σ
ADC
LIMITER
NOTCH
FILTER
AUXSPK[5]
(0x32)
Page 4 of 109
ALC
NMICPGA[1]
(0x2C)
DAC
VREF
MIC+
PMICBSTGAIN[6:4]
(0x2F) = 000
PMICPGA
DACSPK[0]
(0X32)
SPKGAIN[5:0]
(0x36)
SPK3V[2]
(0x31)
MICBIAS
MICBIASEN[4]
(0x2F)
MICROPHONE
BIAS
BYPSPK[1]
(0x32)
(Sidetone) BYPASS
Σ
1.5X
1.0X
SPKOUT+
VDDA
SPKMXEN[2]
(0x03)
1.5X
1.0X
SPKOUT-
R
VREF
PLLEN[5]
(0x01)
R
PLL
CONTROL
INTERFACE
DIGITAL AUDIO
INTERFACE
FS
SO
BCLK
SCLK
SDIO
DACIN
MODE
MCLK
CSb/GPIO
ADCOUT
NAU8812
January 2011
NAU8812
6.
Table of Contents
1.
GENERAL DESCRIPTION ..................................................................................................................................1
2.
FEATURES ......................................................................................................................................................... 1
TABLE OF CONTENTS ......................................................................................................................................5
7.
LIST OF FIGURES ..............................................................................................................................................9
8.
LIST OF TABLES .............................................................................................................................................. 11
9.
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 12
12.3.3. Digital ADC Gain Control .................................................................................................................... 26
12.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) ............................................................................................ 26
12.4.1. Automatic level control (ALC) .............................................................................................................. 26
12.4.1.1.
Normal Mode .............................................................................................................................. 29
12.4.1.2. ALC Hold Time (Normal mode Only) .......................................................................................... 29
12.4.3. Attack Time ......................................................................................................................................... 31
12.4.4. Decay Times ....................................................................................................................................... 31
12.4.6. Zero Crossing...................................................................................................................................... 32
12.5. DAC DIGITAL FILTER BLOCK .................................................................................................................. 33
12.5.4. Hi-Fi DAC De-Emphasis and Gain Control ......................................................................................... 34
12.5.5. Digital DAC Output Peak Limiter ......................................................................................................... 35
12.6. ANALOG OUTPUTS .................................................................................................................................. 36
京公网安备 11010802033920号
EEWORLD
