™
Le79114
VoiceEdge™ Control Processor II
Ve790 Series
APPLICATIONS
Cost effective voice solution for long or short loops
providing POTS and integrated test capabilities
Applications include: IVD, DLC, CO, Voice-enabled
DSLAM, PBX/KTS, MSAP, MSAN
DESCRIPTION
The Le79114 VoiceEdge™ Control Processor II (VCP II) is a
second generation platform that delivers enhanced call control,
self-test and line test capabilities. This latest processor works
with Zarlink Ve790 devices using its SPI interface(s), PCM
port(s), and GPIO. The Le79114 VCP II device provides the
same integrated line-testing and feature-set as the Le79112
VCP device, plus additional capabilities such as 32 channels of
simultaneous DTMF detection and 64 channels of improved
POTS control.
This product enables the design of a low-cost, high-
performance, fully software programmable line interface for
multiple country applications. All AC, DC, signaling parameters
and data are fully programmable. The integrated test capability
is crucial for remote applications where dedicated test
hardware is not cost-effective.
The Le79114 device is provided with extensive software and
support, through the LineCare™ software suite, enabling the
designer to develop a fully programmable solution in the least
amount of time.
FEATURES
Aggregated call control lowers demand on host micro-
processor
— 64 channels of call control
Provides expanded line and circuit testing in
conjunction with Zarlink’s Ve790 Series chipsets
— Provides 32 channels of simultaneous DTMF
— Provides 4 channels of simultaneous line testing
Software interface using VoicePath™ API-II
Software downloadable, field upgradeable, expandable
Serial and parallel host controller interface options
Complete control of up to 16 Quad ISLAC devices
—
Two master SPI ports
— 32 General Purpose I/Os
– 16 configured as chip selects
– 16 configured for interrupts
Two slave PCM highway ports
— Single or dual PCM highways capable of operating
up to 16.384 MHz
— Separate test highway option
Internal PLL and hardware network timing recovery for
creating analog sampling clocks
3.3 V compliant I/O; Internal 3.3 V to 1.8 V linear
regulator for the core logic
RELATED LITERATURE
081130 Le79232 SLIC Device Data Sheet
081185 Le79252 SLIC Device Data Sheet
081256 Le79228 Quad ISLAC™ Device Data Sheet
081190 Le792288 Octal ISLAC™ Device Data Sheet
081507 MPI and PCM Signal Integrity Application Note
081572 Le79114-SW VCP Software Package Data Sheet
VoicePath™ API II Reference Guide
BLOCK DIAGRAM
PCM Highway
PCM bus 2
(optional)
4
Master PCM
or Secondary
Slave
Slave
PCM A/B
PLL
Clock
Generator
Interrupt
Controller
RST
PCM bus
6
SPI1
3
SPI2
4
INT
HBI
21
CONF
3
For Zarlink
debug use
only
To
Host
ORDERING INFORMATION
Device
Le79114KVC
1.
Package
(Green)
1
128-pin TQFP
Packing
2
Tray
To SLAC
devices
SPI1
DSP Core
and
Memory
SPI2
SPI/GPI
Host Bus
Interface
JTAG
CS
16
INT
16
Linear 1.8V
Regulator
GPIO
UART
VDD18CTRL
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Document ID#:
081544
Date:
Apr 23, 2008
Rev:
D
Version:
1
Distribution:
Protected Document
2.
MCU
京公网安备 11010802033920号
EEWORLD
