ZL38065GDG2 datasheet, PDF - EEWORLD Datasheet

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ZL38065GDG2: DescriptionIC voice echo cancel 208lbga; CategoryWireless rf/communication Telecom circuit; File Size641KB，48 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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ZL38065GDG2 Overview

IC voice echo cancel 208lbga

ZL38065GDG2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	BGA
package instruction	LBGA,
Contacts	208
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	17 mm
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.5 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	ISDN ECHO CANCELLER
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm

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ZL38065

32 Channel Voice Echo Canceller

Data Sheet

Features

•

Independent multiple channels of echo

cancellation; from 32 channels of 64 ms to 16

channels of 128 ms with the ability to mix

channels at 128 ms or 64 ms in any combination

Fully compliant to ITU-T G.165, G.168 (2000) and

(2002) specifications

Passed all AT&T voice quality tests for carrier

grade echo canceller systems.

Unparalleled in-system tunability

Sub 50 ms initial convergence times under many

typical network conditions

Fast reconvergence on echo path changes

Patented Advanced Non-Linear Processor with

high quality subjective performance

Superior noise matching algorithm

PCM coding,

µ/A-Law

ITU-T G.711 or sign

magnitude

Per channel Fax/Modem G.164 2100 Hz or G.165

2100 Hz phase reversal Tone Disable

Per channel echo canceller parameters control

Transparent data transfer and mute

Protection against narrow band signal divergence

and instability in high echo environments

•

Ordering Information

ZL38065QCG

ZL38065GDG

ZL38065QCG1

ZL38065GDG2

100

208

100

208

Pin LQFP

Ball LBGA

Pin LQFP*

Ball LBGA**

Trays,

Bake

Drypack

January 2006

•

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

-40°C to +85°C

+9 dB to -12 dB level adjusters (3 dB steps) at all

signal ports

Offset nulling of all PCM channels

Independent Power Down mode for each group of

2 channels for power management

Compatible to ST-BUS and GCI interface at

2 Mbps serial PCM

3.3 V pads and 1.8 V Logic core operation with

5 V tolerant inputs

IEEE-1149.1 (JTAG) Test Access Port

Applications

•

Voice over IP network gateways

Voice over ATM, Frame Relay

T1/E1/J1 multichannel echo cancellation

DD1 (3.3V)

DD2 (1.8 V)

ODE

Echo Canceller Pool

Rin

Sin

MCLK

Fsel

PLL

Serial

Parallel

Group 0

ECA/ECB

Group 1

ECA/ECB

Group 2

ECA/ECB

Group 3

ECA/ECB

Parallel

Serial

Rout

Sout

Group 4

ECA/ECB

Group 5

ECA/ECB

Group 6

ECA/ECB

Group 7

ECA/ECB

Group 8

ECA/ECB

Group 9

ECA/ECB

Group 10

ECA/ECB

Group 11

ECA/ECB

Group 12

ECA/ECB

C4i

F0i

Timing

Unit

Group 13

ECA/ECB

Group 14

ECA/ECB

Group 15

ECA/ECB

Note:

Refer to Figure 4

for Echo Canceller

block diagram

IC0

RESET

Microprocessor Interface

Test Port

DS CS R/W A12-A0 DTA

D7-D0

IRQ TMS TDI TDO TCK TRST

Figure 1 - ZL38065 Device Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL38065

Table of Contents

Data Sheet

1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Double-Talk Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Path Change Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 Non-Linear Processor (NLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.5 Disable Tone Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.6 Instability Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.7 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.8 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.9 Adjustable Level Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10 ITU-T G.168 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.0 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.0 Echo Canceller Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Disable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Enable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0 ZL38065 Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.0 Serial PCM I/O channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.0 Memory Mapped Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Call Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Zarlink Semiconductor Inc.

ZL38065

List of Figures

Data Sheet

Figure 1 - ZL38065 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - 100 Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 3 - 208 Ball LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5 - Sample G.168 Test 2A Convergence Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6 - Disable Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7 -

Normal Device Configuration (64 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8 -

Back-to-Back Device Configuration (64 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9 -

Extended Delay Configuration (128 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams . . . . . . . . . . . . . . . . . . . . 18

Figure 11 - Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12 - Power Up Sequence Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13 - The MU Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14 - ST-BUS Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15 - GCI Interface Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 16 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17 - Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 18 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Zarlink Semiconductor Inc.

ZL38065GDG2 Related Products

	ZL38065GDG2	ZL38065QCG1	ZL38065GDG
Description	IC voice echo cancel 208lbga	IC voice echo cancel 100lqfp	IC voice echo cancel 208lbga
Is it lead-free?	Lead free	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible
Parts packaging code	BGA	QFP	BGA
package instruction	LBGA,	LFQFP,	17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
Contacts	208	100	208
Reach Compliance Code	compli	compli	unknow
JESD-30 code	S-PBGA-B208	S-PQFP-G100	S-PBGA-B208
length	17 mm	14 mm	17 mm
Number of functions	1	1	1
Number of terminals	208	100	208
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LFQFP	LBGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	225
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.6 mm	1.5 mm
Nominal supply voltage	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
Telecom integrated circuit types	ISDN ECHO CANCELLER	ISDN ECHO CANCELLER	ISDN ECHO CANCELLER
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	GULL WING	BALL
Terminal pitch	1 mm	0.5 mm	1 mm
Terminal location	BOTTOM	QUAD	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30
width	17 mm	14 mm	17 mm
Maker	Microsemi	-	Microsemi
JESD-609 code	e1	-	e0
Terminal surface	TIN SILVER COPPER	-	TIN LEAD

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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