• Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f
max
• Ultra-low standby power
• Easy memory expansion with CE
1
, CE
2
, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA,
44-pin TSOPII, and Pb-free 48-pin TSOPI
Functional Description
[1]
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table for a complete description
of read and write modes.
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
DATA-IN DRIVERS
512K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
CE
2
CE
1
Power-down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines,
which is available at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 8, 2006
[+] Feedback
CY62157DV30 MoBL
®
Product Portfolio
Power Dissipation
Operating I
CC
, (mA)
V
CC
Range (V)
Product
CY62157DV30L
Range
Industrial
Min.
2.2
2.2
2.2
2.2
Typ.
[2]
3.0
3.0
3.0
3.0
Max.
3.6
3.6
3.6
3.6
Speed
(ns)
45, 55, 70
45, 55, 70
55
55
f = 1MHz
Typ.
[2]
1.5
1.5
1.5
1.5
Max.
3
3
3
3
f = f
max
Typ.
[2]
12
12
12
12
Max.
20
15
15
20
Standby I
SB2
,
(µA)
Typ.
[2]
2
2
2
2
Max.
20
8
8
50
CY62157DV30LL Industrial
CY62157DV30LL Automotive-A
CY62157DV30L
Automotive-E
Pin Configuration
[4, 5, 6]
48-Pin TSOP I Pinout
Top View
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
48-Ball FBGA Pinout
Top View
1
BLE
I/O
8
I/O
9
V
SS
V
CC
2
OE
BHE
I/O
10
I/O
11
3
A
0
A
3
A
5
A
17
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
Vcc
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
44-pin TSOP II Pinout
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
18
A
17
A
16
A
15
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
I/O
12
DNU
A
14
A
12
A
9
I/O
14
I/O
13
I/O
15
A
18
NC
A
8
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
A
12
A
13
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
3. NC pins are not internally connected on the die.
4. DNU pins have to be left floating.
5. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19, while
BHE, BLE and I/O8 to I/O14 pins are not used.
6. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *H
Page 2 of 12
[+] Feedback
CY62157DV30 MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground
Potential ............................................ –0.3V to V
Latch-up Current...................................................... >200 mA
Operating Range
Device
CY62157DV30L
CY62157DV30LL
CY62157DV30LL Automotive-A –40°C to +85°C
CY62157DV30L
Automotive-E –40°C to +125°C
Range
Industrial
Ambient
Temperature
(T
A
)
–40°C to +85°C
V
CC
[10]
2.20V
to
3.60V
........................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics
Over the Operating Range
-45, -55, -70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
Ind’l/Auto-A
[7]
Auto-E
[7]
I
OZ
GND < V
O
< V
CC
, Output Disabled
Ind’l/Auto-A
[7]
Auto-E
[7]
V
CC
= V
CCmax
L
I
OUT
= 0 mA LL
CMOS levels
L
LL
I
SB1
Automatic CE
Power-Down
Current — CMOS
Inputs
Automatic CE
Power-Down
Current -CMOS
Inputs
L
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V
Ind’l
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V)
[7]
LL
f = f
MAX
(Address and Data Only), f = 0 Ind’l/Auto-A
(OE, WE, BHE and BLE), V
CC
= 3.60V Auto-E
[7]
L
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
Ind’l
[7]
L
Ind’l/Auto-A
[7]
LL
Auto-E
[7]
L
Test Conditions
V
CC
= 2.20V
V
CC
= 2.70V
V
CC
= 2.20V
V
CC
= 2.70V
1.8
2.2
–0.3
–0.3
–1
–4
–1
–4
12
12
1.5
1.5
2
2
Min. Typ.
[2]
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
+4
+1
+4
20
15
3
3
20
8
50
2
2
20
8
50
µA
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
µA
I
CC
f = f
MAX
= 1/t
RC
f = 1 MHz
I
SB2
Capacitance
[11, 12]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
Notes:
7. Automotive-A and Automotive-E available only in -55.
8. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
9. V
IH(max)
= V
CC
+0.75V for pulse duration less than 20 ns.
10. Full device AC operation assumes a 100
µs
ramp time from 0 to V
CC
(min) and 200
µs
wait time after V
CC
stabilization.
11. Tested initially and after any design or process changes that may affect these parameters.
12. The input capacitance on the CE
2
pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF.
Document #: 38-05392 Rev. *H
Page 3 of 12
[+] Feedback
CY62157DV30 MoBL
®
Thermal Resistance
[11]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
FBGA
39.3
9.69
TSOP II
35.62
9.13
TSOP I
36.9
10.05
Unit
°C/W
°C/W
AC Test Loads and Waveforms
[13]
R1
V
CC
OUTPUT
30 pF / 50 pF
V
CC
GND
R2
Rise Time = 1 V/ns
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Ind’l (L)
Ind’l/Auto-A (LL)
Auto-E (L)
0
t
RC
Conditions
Min.
1.5
10
4
25
ns
ns
Typ.
[2]
Max.
Unit
V
µA
t
CDR[11]
t
R[14]
Chip Deselect to Data
Retention Time
Operation Recovery Time
Data Retention Waveform
[15]
V
CC
CE
1
or
BHE
.
BLE
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 1.5 V
V
CC
, min.
t
R
or
CE
2
Notes:
13. Test condition for the 45 ns part is a load capacitance of 30 pF.
14. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
Document #: 38-05392 Rev. *H
Page 4 of 12
[+] Feedback
CY62157DV30 MoBL
®
Switching Characteristics
Over the Operating Range
[16]
45 ns
[13]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[19]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[17, 18]
WE HIGH to Low-Z
[17]
10
45
40
40
0
0
35
40
25
0
15
10
55
40
40
0
0
40
40
25
0
20
10
70
60
60
0
0
45
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[17]
OE HIGH to High Z
[17, 18]
CE
1
LOW and CE
2
HIGH to Low Z
[17]
55 ns
Min.
55
Max.
70 ns
Min.
70
55
70
10
55
25
70
35
5
20
25
10
20
25
0
55
55
70
70
10
20
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
45
Max.
45
10
45
25
5
15
10
20
0
45
45
10
15
10
0
10
5
10
CE
1
HIGH and CE
2
LOW to High Z
[17, 18]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[17]
BLE/BHE HIGH to HIGH Z
[17, 18]
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
17. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
18. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
19. The internal Write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
京公网安备 11010802033920号
EEWORLD
