114SBFTFREQ datasheet, PDF - EEWORLD Datasheet

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114SBFTFREQ: DescriptionCMOS Output Clock Oscillator, 8MHz Min, 38.88MHz Max, ROHS COMPLIANT, DIP-14/4; CategoryPassive components oscillator; File Size52KB，2 Pages; ManufacturerCTS; Environmental Compliance

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114SBFTFREQ Overview

CMOS Output Clock Oscillator, 8MHz Min, 38.88MHz Max, ROHS COMPLIANT, DIP-14/4

114SBFTFREQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Reach Compliance Code	compli
Ageing	2.5 PPPM/20 YEAR
Frequency Adjustment - Mechanical	NO
frequency stability	0.25%
Frequency Stability - Voltage	0.05 ppm
input power	1.5 W
JESD-609 code	e2
Manufacturer's serial number	114
Installation features	THROUGH HOLE MOUNT
Maximum operating frequency	38.88 MHz
Minimum operating frequency	8 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
Output load	10 KOHM, 15 pF
Oven power supply voltage	5V
physical size	20.32mm x 12.7mm x 11.05mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
Terminal surface	Tin/Silver (Sn/Ag)
Preheating power	3.5 W
Maximum warm-up time	5 Minute
Base Number Matches	1

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Model 114

Dual-In-Line Stratum 3 OCXO

♦

Frequency Stability to Stratum 3 of GR-1244

♦

Low Cost ASIC Based Design

♦

Very Low Phase Jitter: < 1 pSec

♦

+3.3Vdc or +5.0Vdc Operation

♦

Precision Low Aging “AT” Cut Crystal

♦

Through-Hole or Surface Mount Configuration

♦

6/6 RoHS Compliant

Electrical Characteristics

Parameter

Power Requirements

Power Supply

Turn-On Power

Steady State Power

max

Sym

Conditions

114L

114S

Vcc=Max.

Std. Load

Vcc=Max.

Std. Load

@ +25°C

To within

0.3ppm

@ +25°C

Min

3.135

4.75

Typical

3.30

5.0

3.5

1.5

Max

3.465

5.25

4.0

Unit

Vdc

Warm-Up Time

Frequency Stabilities

Center Frequency

Twu

minutes

nom

Initial Tolerance

Freq. vs. Temp.

Freq. vs. Voltage

Freq. vs Time (Aging)

24 Hour Holdover

Stability

Total Free-Running

Accuracy

Electronic Frequency

Adjust (Optional)

Waveform: CMOS

Output

Symmetry

Amplitude

Rise/Fall Times

Load

Phase Noise

@ f

=20MHz

cal

∆f/∆Temp

∆f/∆Vcc

∆f/∆Time

∆f/24Hr

∆f/Life

∆f/Vc

Ta=+25°C

(At time of Shipment)

0° to +70°C

-40° to +85°C

Vcc

±5%

Per day

20 years

Inclusive of Temp.,

Supply Variation and

24Hrs. Aging

All Cond. for 20 Yrs.

(Ref. to f

nom

)

min

@ Vc=0V

max

@ Vc=Vcc

nom

@Vc=0.5Vcc

12.8

16.384

19.44

±0.1

±0.075

±0.150

0.05

±0.005

±2.5

±0.20

38.88

MHz

ppm

±0.125

±0.250

ppm

±0.37

±4.6

ppm

±9.2

Sym

tr, tf

@ 50% Level

Logic “1”

Logic “0”

20% to 80%

Output to Ground

Offset = 10Hz

100Hz

1kHz

10kHz

100kHz

12kHz to 20MHz

Bandwidth

0.9Vcc

0.1Vcc

10kΩ // 15pF

-80

-115

-135

-140

-143

Phase Jitter

1.0

dBc/Hz

ps RMS

♦♦♦

CTS

♦

171 Covington Dr.

♦

Bloomingdale, IL 60108

♦

800-757-6686

♦

www.ctscorp.com

♦♦♦

Document No. 114 Data Sheet

Page 1 of 2

Rev X8

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