MT45W2MW16PGA-70 IT TR datasheet, PDF

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MT45W2MW16PGA-70 IT TR: DescriptionIC psram 32mbit 70ns 48vfbga; Categorystorage; File Size732KB，26 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT45W2MW16PGA-70 IT TR Overview

IC psram 32mbit 70ns 48vfbga

MT45W2MW16PGA-70 IT TR Parametric

Parameter Name	Attribute value
Datasheets
MT45W2MW16PGA
Product Photos
48 VFBGA Package
Standard Package	1,000
Category	Integrated Circuits (ICs)
Family	Memory
Packaging	Tape & Reel (TR)
Format - Memory	RAM
Memory Type	PSRAM (Page)
Memory Size	32M (2M x 16)
Speed	70ns
Interface	Parallel
Voltage - Supply	1.7 V ~ 1.95 V
Operating Temperature	-40°C ~ 85°C
Package / Case	48-VFBGA
Supplier Device Package	48-VFBGA (6x8)
Other Names	557-1317-2MT45W2MW16PGA70ITTR

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32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Features

Async/Page CellularRAM™ 1.0 Memory

MT45W2MW16PGA

Features

• Asynchronous and page mode interface

• Random access time: 70ns

• V

, V

Q voltages:

–

1.7–1.95V V

–

1.7–3.6V V

• Page mode read access:

–

16-word page size

–

Interpage read access: 70ns

–

Intrapage read access: 20ns

• Low power consumption:

–

Asynchronous READ: <20mA

–

Intrapage READ: <15mA

–

Standby: <110µA

–

Deep power-down: <10µA (TYP at 25°C)

• Low-power features:

–

Temperature-compensated refresh (TCR)

–

On-chip temperature sensor

–

Partial-array refresh (PAR)

–

Deep power-down (DPD) mode

Figure 1:

48-Ball VFBGA Ball Assignment

LB#

OE#

ZZ#

DQ8

UB#

CE#

DQ0

DQ9

DQ10

DQ1

DQ2

VssQ

DQ11

A17

DQ3

Vcc

VccQ

DQ12

A16

DQ4

Vss

DQ14

DQ13

A14

A15

DQ5

DQ6

DQ15

A19

A12

A13

WE#

DQ7

A18

A10

A11

A20

Options

Designator

• Configuration

• 2 Meg x 16

MT45W2MW16P

• Package

• 48-ball VFBGA (green)

• Access time

• 70ns

–70

• Operating temperature range

• Wireless (–30°C to +85°C)

• Industrial (–40°C to +85°C)

Notes: 1. –30°C exceeds the CellularRAM Workgroup

1.0 specification of –25°C.

Top View

(Ball Down)

Part Number Example:

MT45W2MW16PGA-70WT

PDF: 09005aef82832fa7 / Source: 09005aef82832f97

32mb_asyncpage_cr1_0_p24z_1.fm - Rev. B 5/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PDF: 09005aef82832fa7 / Source: 09005aef82832f97

32mb_asyncpage_cr1_0_p24zTOC.fm - Rev. B 5/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

List of Figures

Figure 1:

Figure 2:

Figure 3:

Figure 4:

Figure 5:

Figure 6:

Figure 7:

Figure 8:

Figure 9:

Figure 10:

Figure 11:

Figure 12:

Figure 13:

Figure 14:

Figure 15:

Figure 16:

Figure 17:

Figure 18:

Figure 19:

Figure 20:

Figure 21:

Figure 22:

Figure 23:

Figure 24:

48-Ball VFBGA Ball Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Functional Block Diagram 2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Page READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Software Access PAR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Load Configuration Register Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Software Access Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Software Access Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Configuration Register Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Power-Up Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Deep Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Single READ Operation (WE# = V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Page Mode READ Operation (WE# = V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

WRITE Cycle (WE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

WRITE Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

WRITE Cycle (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PDF: 09005aef82832fa7 / Source: 09005aef82832f97

32mb_asyncpage_cr1_0_p24zLOF.fm - Rev. B 5/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

List of Tables

Table 1:

Table 2:

Table 3:

Table 4:

Table 5:

Table 6:

Table 7:

Table 8:

Table 9:

Table 10:

Table 11:

Table 12:

Table 13:

VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

32Mb Address Patterns for PAR (CR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Partial-Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Capacitance Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PDF: 09005aef82832fa7 / Source: 09005aef82832f97

32mb_asyncpage_cr1_0_p24zLOT.fm - Rev. B 5/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory

General Description

Micron

CellularRAM™ products are high-speed, CMOS PSRAM memories developed

for low-power, portable applications. The MT45W2MW16P is a 32Mb DRAM core device

organized as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous

memory interface found on other low-power SRAM or pseudo-SRAM offerings.

A user-accessible configuration register (CR) defines how the CellularRAM device

performs on-chip refresh and whether page mode read accesses are permitted. This

updated at any time during normal operation.

For seamless operation on an asynchronous memory bus, CellularRAM products incor-

porate a transparent self-refresh mechanism. The hidden refresh requires no additional

support from the system memory controller and has no significant impact on device

read/write performance.

Special attention has been focused on current consumption during self refresh. Cellu-

larRAM products include three system-accessible mechanisms to minimize refresh

current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the

refresh rate to match the device temperature. The refresh rate decreases at lower

temperatures to minimize current consumption during standby. Setting sleep enable

(ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep

power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains

essential data. DPD halts refresh operation altogether and is used when no vital infor-

mation is stored in the device. The system-configurable refresh mechanisms are

accessed through the CR.

Functional Block Diagram

Figure 2:

Functional Block Diagram 2 Meg x 16

A[20:0]

Address Decode

Logic

2,048K x 16

DRAM

Memory

Array

Configuration

Input/

Output

MUX

and

Buffers

DQ[7:0]

DQ[15:8]

CE#

WE#

OE#

UB#

LB#

ZZ#

Control

Logic

Note:

Functional block diagrams illustrate simplified device operation. See ball description table,

bus operations table, and timing diagrams for detailed information.

PDF: 09005aef82832fa7 / Source: 09005aef82832f97

32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT45W2MW16PGA-70 IT TR Related Products

	MT45W2MW16PGA-70 IT TR	MT45W2MW16PGA-70 IT	MT45W2MW16PGA-70 WT TR
Description	IC psram 32mbit 70ns 48vfbga	IC psram 32mbit 70ns 48vfbga	IC psram 32mbit 70ns 48vfbga
Standard Package	1,000	1,000	1,000
Category	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)
Family	Memory	Memory	Memory
Packaging	Tape & Reel (TR)	Tray	Tape & Reel (TR)
Format - Memory	RAM	RAM	RAM
Memory Type	PSRAM (Page)	PSRAM (Page)	PSRAM (Page)
Memory Size	32M (2M x 16)	32M (2M x 16)	32M (2M x 16)
Speed	70ns	70ns	70ns
Interface	Parallel	Parallel	Parallel
Voltage - Supply	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V
Operating Temperature	-40°C ~ 85°C	-40°C ~ 85°C	-30°C ~ 85°C
Package / Case	48-VFBGA	48-VFBGA	48-VFBGA
Supplier Device Package	48-VFBGA (6x8)	48-VFBGA (6x8)	48-VFBGA (6x8)
Other Names	557-1317-2MT45W2MW16PGA70ITTR	-	557-1316-2

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