Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0×C to +70×C
–40×C to +85×C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW
Voltage
[1]
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
Input Load Current
Output Leakage Current
Test
Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–1
–1
7C1020BN-12
Min.
2.4
0.4
6.0
0.8
+1
+1
–300
140
20
3
L
0.5
2.2
–0.5
–1
–1
Max.
7C1020BN-15
Min.
2.4
0.4
6.0
0.8
+1
+1
–300
130
20
3
0.5
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
Output Short Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
V
CC
Operating Supply Current V
CC
= Max., I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
Automatic CE Power-Down
Current—TTL Inputs
Automatic CE Power-Down
Current—CMOS Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V,
f=0
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06443 Rev. **
Page 2 of 8
[+] Feedback
CY7C1020BN
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R 481Ω
R 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
167
R2
255Ω
GND
3.0V
90%
10%
ALL INPUT PULSES
90%
10%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
1.73V
30 pF
Switching Characteristics
[5]
Over the Operating Range
7C1020BN-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
7C1020BN-15
Min.
15
Max.
Unit
ns
15
3
15
7
0
7
3
7
0
15
7
0
7
15
10
10
0
0
10
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
9
ns
ns
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low
Z
[6]
Min.
12
Max.
12
3
12
6
0
6
3
6
0
12
6
0
6
12
9
8
0
0
8
6
0
3
6
8
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document #: 001-06443 Rev. **
Page 3 of 8
[+] Feedback
CY7C1020BN
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[10, 11]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
IICC
CC
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06443 Rev. **
Page 4 of 8
[+] Feedback
CY7C1020BN
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
BW
BHE, BLE
t
SD
DATA I/O
t
HD
t
HA
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
PWE
WE
t
SCE
CE
t
SD
DATA I/O
t
HD
t
HA
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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