PHT
www.vishay.com
Vishay Sfernice
High Stability - High Temperature (230 °C)
Thin Film Wraparound Chip Resistors, Sulfur Resistant
FEATURES
• Operating temperature range:
-55 °C; +215 °C
• Storage temperature: -55 °C; +230 °C
• Gold terminations (< 1 μm thick)
• 5 sizes available (0402, 0603, 0805, 1206,
2010); other sizes upon request
• Temperature coefficient down to 15 ppm
(-55 °C; +215 °C)
• Tolerance down to 0.05 %
• Load life stability: 0.35 % max. after 2000 h at 220 °C
(ambient) at Pn
• Shelf life stability: 0.7 % typ. (1 % max.) after 15 000 h at
230 °C
• SMD wraparound
• TCR remains constant after long term storage at 230 °C
(15 000 h)
• Sulfur resistant (per ASTM B809-95 humid vapor test)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
DESIGN SUPPORT TOOLS
Models
Available
click logo to get started
INTRODUCTION
For applications such as down hole applications, the need
for parts able to withstand very severe conditions
(temperature as high as 215 °C powered or up to 230 °C
un-powered) has leaded Vishay Sfernice to push out the
limit of the thin film technology.
Designers might read the application note: Power
Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays
(P, PRA etc…) (High Temperature Application)
www.vishay.com/doc?53047
in conjunction with this
datasheet to help them to properly design their PCBs and
get the best performances of the PHT.
Vishay Sfernice R&D engineers will be willing to support any
customer design considerations.
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
PHT0402
PHT0603
PHT0805
PHT1206
PHT2010
SIZE
0402
0603
0805
1206
2010
RESISTANCE
RANGE
10 to 130K
10 to 320K
10 to 720K
10 to 2.7M
10 to 7.5M
RATED POWER
(1)(2)
P
215 °C
W
0.0189
0.0375
0.06
0.1
0.2
(4)
LIMITING ELEMENT
VOLTAGE
V
50
75
150
200
300
TOLERANCE
(2)
±%
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
TEMPERATURE
COEFFICIENT
(3)
± ppm/°C
10, 15, 25, 30, 50, 55
10, 15, 25, 30, 50, 55
10, 15, 25, 30, 50, 55
10, 15, 25, 30, 50, 55
10, 15, 25, 30, 50, 55
Notes
(1)
For power handling improvement, please refer to application note 53047: “Power Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays (High Temperature Applications)”
www.vishay.com/doc?53047
and consult Vishay Sfernice
(2)
See Table 2 on next page
(3)
See Table 1 on next page
(4)
It is possible to dissipate up to 0.3 W, but there will be an additional drift of 0.1 % after load life
CLIMATIC SPECIFICATIONS
Operating temperature range
Storage temperature range
-55 °C; +215 °C
-55 °C; +230 °C
MECHANICAL SPECIFICATIONS
Substrate
Resistive Element
Passivation
Protection
Terminations
Alumina
Nichrome (NiCr)
Silicon nitride (Si
3
N
4
)
Epoxy + silicone
Gold (< 1 μm) over nickel barrier
PERFORMANCE VS. HUMID SULFUR VAPOR
Test conditions
Test results
Revision: 03-Jan-2019
50 °C ± 2 °C, 85 % ± 4 % RH,
exposure time 500 h
Resistance drift < (0.05 %
R
+ 0.05
),
no corrosion products observed
Note
• For other terminations, please consult
Document Number: 53050
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHT
www.vishay.com
Vishay Sfernice
TABLE 1 - TEMPERATURE COEFFICIENT
Y
10 ppm/°C
15 ppm/°C
25 ppm/°C
30 ppm/°C
50 ppm/°C
55 ppm/°C
-55 °C; +155 °C
-55 °C; +215 °C
-55 °C; +155 °C
-55 °C; +215 °C
-55 °C; +155 °C
-55 °C; +215 °C
E
H
TABLE 2 - BEST TOLERANCE AND TCR VS. OHMIC VALUE
SERIES
RANGE ()
10 to 50
0402
> 50 to 90K
> 90K to 130K
10 to 50
0603
> 50 to 210K
> 210K to 320K
10 to 50
0805
> 50 to 480K
> 480K to 720K
10 to 50
1206
> 50 to < 1.8M
> 1.8M to 2.7M
10 to 50
2010
> 50 to 5M
> 5M to 7.5M
TOL. (± %)
0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.1; 0.5; 1
0.05; 0.1; 0.5; 1
0.05; 0.1; 0.5; 1
TCR CODE
Y; E; H
Y; E; H
E; H
Y; E; H
Y; E; H
E; H
Y; E; H
Y; E; H
E; H
Y; E; H
Y; E; H
E; H
Y; E; H
Y; E; H
E; H
PHT STABILITY CURVE
High Temperature Drift vs. Time
2.0
1.8
1.6
1000
1st line
2nd line
10000
POWER DERATING CURVE
Power Derating Curve
1.2
1.0
2nd line
Rated Power (W)
PHT2010
PHT1206
PHT0805
PHT0603
PHT0402
10000
1.4
2nd line
Drift (%)
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.6
0.4
0.2
100
With Pd
(T
j
= 230 °C)
100
10
4000
8000
Time (h)
12 000
0
0
50
100
150
200
250
Ambient Temperature (°C)
10
Note
• Stability will be dependent on resistivity of resistor.
Above curves are worst case.
Revision: 03-Jan-2019
Document Number: 53050
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
1st line
2nd line
T = 230 °C
T = 215 °C
T = 200 °C
T = 185 °C
0.8
1000
PHT
www.vishay.com
DIMENSIONS
in millimeters (inches)
A
D
D
Vishay Sfernice
C
B
E
E
A
MAX. TOL.
+0.152 (+0.006)
MIN. TOL.
-0.152 (-0.006)
NOMINAL
0402
0603
0805
1206
2010
1.00 (0.039)
1.52 (0.060)
1.91 (0.075)
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+0.127 (+0.005)
MIN. TOL.
-0.127 (-0.005)
NOMINAL
0.60 (0.024)
0.85 (0.033)
1.27 (0.050)
1.60 (0.063)
2.54 (0.100)
Termination G:
0.4 (0.016)
± 0.051 (0.002)
0.13 (0.005)
0.40 (0.016)
0.48 (0.019)
Termination N:
0.5 (0.02)
± 0.127 (0.005)
D/E
C
CASE SIZE
NOMINAL
0.25 (0.010)
0.38 (0.015)
TOLERANCE
0.1 (0.004)
SUGGESTED LAND PATTERN (TO IPC-7351A)
G
min.
X
max.
Z
max.
DIMENSIONS (in millimeter)
CHIP SIZE
Z
max.
0402
0603
0805
1206
2010
1.55
2.37
2.76
3.91
5.93
G
min.
0.15
0.35
0.74
1.85
3.71
X
max.
0.73
0.98
1.40
1.73
2.67
Caution:
Performances obtained with following mounting conditions:
PCB: polyimide
Solder paste: PbSnAg (93.5/5/1.5)
Revision: 03-Jan-2019
Document Number: 53050
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHT
www.vishay.com
POPULAR OPTIONS
It is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged terminations:
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink
(see application note: 53048 “Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film)”
www.vishay.com/doc?53048.
Option to order: 0063 (applies to size 1206 / 2010).
Vishay Sfernice
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoated
ceramic
Enlarged
termination
B
F
D
E
A
CASE SIZE
MAX. TOL.
+0.152
MIN. TOL.
-0.152
NOMINAL
1206
2010
3.06
5.08
B
MAX. TOL.
+0.127
MIN. TOL.
-0.127
NOMINAL
1.60
2.54
E
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
0.40
0.48
D
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
1.215
2.25
NOMINAL
0.63
F
MIN.
0.50
MAX.
0.76
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
CHIP SIZE
1206
2010
DIMENSIONS (in millimeter)
Z
max.
3.91
5.93
G
min.
0.50
X
max.
1.73
2.67
Revision: 03-Jan-2019
Document Number: 53050
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHT
www.vishay.com
PACKAGING
ESD packaging available: waffle-pack and plastic tape and
reel (low conductivity). Paper tape available upon request
(for sizes 0402, 0603, 0805 and 1206).
NUMBER OF PIECES PER PACKAGE
SIZE MOQ
0402
0603
0805
1206
2010
Note
(1)
12 mm on request
100
140
60
100
100
WAFFLE PACK
2" × 2"
TAPE AND REEL
MIN.
MAX.
5000
8 mm
4000
1000
8 mm
(1)
TAPE
WIDTH
Vishay Sfernice
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code.
Tape and Reel
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered is between the MOQ and the
maximum reel capacity, only one reel is provided.
When several reels are needed for ordered quantity
within MOQ and maximum reel capacity: please consult
Vishay Sfernice for specific ordering code.
GLOBAL PART NUMBER INFORMATION
Global Part Numbering: PHT1206Y1001BGT063
P
H
T
1
2
0
6
Y
1
0
0
1
B
G
T
0
6
3
GLOBAL
MODEL
PHT
SIZE
0402
0603
0805
1206
2010
TCR
Y
E
H
VALUE
The first three digits are
significant figures and
the last digit specifies
the number of zeros to
follow, R designates
decimal point
10R0
= 10
3901
= 3900
1004
= 1 M
TOLERANCE
W
= 0.05 %
B
= 0.1 %
D
= 0.5 %
F
=1%
TERMINATION
G
= gold
N
= tin / silver
(1)
PACKAGING
For more
information see
codification of
Packaging table
OPTION
Leave blank
if no option
Note
(1)
For usage at temperatures up to 200 °C maximum N (tin/silver termination are available upon request)
CODIFICATION OF PACKAGING
CODE 18
PACKAGING
WAFFLE PACK
W
100 min., 1 mult
WA
100 min., 100 mult (available only on size 1206)
PLASTIC TAPE (in standard for all sizes)
T
100 min., 1 mult
TA
100 min., 100 mult
TB
250 min., 250 mult
TC
500 min., 500 mult
TD
1000 min., 1000 mult
2500min., 2500 mult
TE
TF
Full tape (quantity depending on size of chips)
PAPER TAPE (Available for 0402, 0603, 0805 and 1206. Please consult Vishay Sfernice for 2010 size.)
PT
100 min., 1 mult
PA
100 min., 100 mult
PB
250 min., 250 mult
PC
500 min., 500 mult
PD (not available for size 0402)
1000 min., 1000 mult
PE (not available for size 0402)
2500min., 2500 mult
PF (not available for size 0402)
Full tape (quantity depending on size of chips)
Revision: 03-Jan-2019
Document Number: 53050
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
ADI Reference Circuit
京公网安备 11010802033920号
EEWORLD
