PHD96NQ03LT
N-channel TrenchMOS logic level FET
Rev. 06 — 15 March 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge
1.3 Applications
DC-to-DC convertors
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 5 V;
see
Figure 1
and
3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
25
75
115
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 50 A;
V
DS
= 15 V; T
j
= 25 °C;
see
Figure 11
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 9
V
GS
= 5 V; I
D
= 25 A;
T
j
= 25 °C;
see
Figure 9
and
10
-
8.4
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
-
4.2
5.6
4.95
7.5
mΩ
mΩ
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
2
1
3
[1]
Simplified outline
mb
Graphic symbol
D
G
mbb076
S
SOT428 (DPAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PHD96NQ03LT
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
Version
SOT428
Type number
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 15 March 2010
2 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 5 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1
and
3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≤
175 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
25
25
20
65
75
240
115
175
175
75
240
185
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 43 A; V
sup
≤
15 V;
drain-source avalanche R
GS
= 50
Ω;
t
p
= 0.25 ms; unclamped
energy
non-repetitive
V
GS
= 10 V; V
sup
≤
15 V; R
GS
= 50
Ω;
drain-source avalanche T
j(init)
= 25 °C; unclamped
current
I
DS(AL)S
-
75
A
120
I
der
(%)
80
03af09
120
P
der
(%)
80
03aa16
40
40
0
0
0
50
100
150
200
T
mb
(°C)
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 15 March 2010
3 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
03af11
Limit R
DSon
= V
DS
/I
D
t
p
= 10 µs
100 µs
1 ms
DC
10
10 ms
100 ms
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
1.3
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
thermal resistance from minimum footprint; mounted on a
junction to ambient
printed-circuit board
R
th(j-a)
-
75
-
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
−1
0.1
0.05
0.02
10
−2
single pulse
10
−3
10
−5
t
p
T
P
03af10
δ
=
t
p
T
t
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 15 March 2010
4 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 25 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 25 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= 15 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -15 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
see
Figure 9
and
10
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 9
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 9
and
10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 25 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 10 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 25 V; T
j
= 25 °C
V
DS
= 15 V; R
L
= 1.2
Ω;
V
GS
= 5 V;
R
G(ext)
= 5.6
Ω;
T
j
= 25 °C; I
D
= 12.5 A
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
I
D
= 50 A; V
DS
= 15 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
-
26.7
8.5
8.4
2200
725
290
18
70
75
70
0.9
43
40
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
22
25
0.5
-
1
-
-
-
-
-
-
-
Typ
-
-
-
-
1.5
0.05
-
10
10
10
4.2
5.6
Max
-
-
-
2.3
2
1
500
100
100
13.5
4.95
7.5
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 15 March 2010
5 of 13
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