16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P
The ISLA216P is a family of low power, high performance
16-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA216P is part of a pin-compatible portfolio
of 12 to 16-bit A/Ds with maximum sample rates ranging from
130MSPS to 500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA216P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Features
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs Clock jitter
• 700MHz Bandwidth
• Programmable built-in test patterns
• Multi-ADC support
- SPI Programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200
µs
Sleep wake-up time
• Data output clock
• DDR LVDS-compatible or LVCMOS outputs
• Selectable Clock Divider
Key Specifications
• SNR @ 250/200/130MSPS
- 75.0/76.6/77.5dBFS f
IN
= 30MHz
- 72.1/72.6/72.4dBFS f
IN
= 363MHz
• SFDR @ 250/200/130MSPS
- 87/91/96dBc f
IN
= 30MHz
- 81/80/82dBc f
IN
= 363MHz
• Total Power Consumption = 786mW @ 250MSPS
Applications
• Radar array processing
• Software defined radios
• Broadband communications
• High-performance data acquisition
• Communications test equipment
CLKDIVRSTN
CLKDIVRSTP
Pin-Compatible Family
OVDD
CLKDIV
AVDD
MODEL
ISLA216P25
ISLA216P20
CLKOUTP
CLKOUTN
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
CLKP
CLKN
CLOCK
MANAGEMENT
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
VINP
SHA
VINN
+
–
16-BIT
250 MSPS
ADC
D[14:0]P
DIGITAL
ERROR
C R EC N
O R TIO
D[14:0]N
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
VCM
SPI
CONTROL
RESETN
NAPSLP
December 10, 2012
FN7574.2
1
RLVDS
OVSS
AVSS
CSB
SCLK
SDIO
SDO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA216P
Pin Configuration - LVDS MODE
ISLA216P
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
SDO
DNC
DNC
CSB
D0N
D2N
D4N
55
54 DNC
53 DNC
52 D6P
51 D6N
50 DNC
49 DNC
48 CLKOUTP
47 CLKOUTN
46 RLVDS
45 OVSS
44 D8P
43 D8N
42 DNC
41 DNC
40 D10P
39 D10N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
D0P
D2P
72
DNC
DNC
NAPSLP
VCM
AVSS
AVDD
AVSS
VINN
VINN
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
VINP 10
VINP 11
AVSS 12
AVDD 13
AVSS 14
CLKDIV 15
IPTAT 16
DNC 17
Connect Thermal Pad to AVSS
RESETN 18
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
DNC
29
DNC
30
D14N
31
D14P
32
OVDD
33
DNC
34
DNC
35
D12N
36
D12P
D4P
38 DNC
37 DNC
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
1, 2, 17, 28, 29, 33, 34, 37,
38, 41, 42, 49, 50, 53, 54,
57, 58
6, 13, 19, 20, 21, 70, 71, 72
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
LVDS PIN NAME
DNC
Do Not Connect
LVDS PIN FUNCTION
AVDD
AVSS
OVDD
OVSS
NAPSLP
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
2
FN7574.2
December 10, 2012
ISLA216P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
4
8, 9
10, 11
15
16
18
22, 23
24, 25
30
31
35
36
39
40
43
44
46
47, 48
51
52
55
56
59
60
63
64
66
67
68
69
Exposed Paddle
LVDS PIN NAME
VCM
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D14N
D14P
D12N
D12P
D10N
D10P
D8N
D8P
RLVDS
CLKOUTN, CLKOUTP
D6N
D6P
D4N
D4P
D2N
D2P
D0N
D0P
SDO
CSB
SCLK
SDIO
AVSS
Common Mode Output
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
DDR Logical Bits 14, 15 Complement
DDR Logical Bits 14, 15 True
DDR Logical Bits 12, 13 Complement
DDR Logical Bits 12, 13 True
DDR Logical Bits 10, 11 Complement
DDR Logical Bits 10, 11 True
DDR Logical Bits 8, 9 Complement
DDR Logical Bits 8, 9 True
LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)
LVDS Clock Output Complement, True
DDR Logical Bits 6, 7 Complement
DDR Logical Bits 6, 7 True
DDR Logical Bits 4, 5 Complement
DDR Logical Bits 4, 5 True
DDR Logical Bits 2, 3 Complement
DDR Logical Bits 2, 3 True
DDR Logical Bits 0, 1 Complement
DDR Logical Bits 0, 1 True
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
(Continued)
LVDS PIN FUNCTION
3
FN7574.2
December 10, 2012
ISLA216P
Pin Configuration - CMOS MODE
ISLA216P
(72 LD QFN)
TOP VIEW
OVDD
AVDD
AVDD
AVDD
OVSS
OVSS
SDIO
SCLK
DNC
DNC
DNC
DNC
DNC
55
54
DNC
53
DNC
52
D6
51
DNC
50
DNC
49
DNC
48
CLKOUT
47
DNC
46
RLVDS
45
OVSS
44
D8
43
DNC
42
DNC
41
DNC
40
D10
39
DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
SDO
CSB
D0
D2
72
DNC
DNC
NAPSLP
VCM
AVSS
AVDD
AVSS
VINN
VINN
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VINP
10
VINP
11
AVSS
12
AVDD
13
AVSS
14
CLKDIV
15
IPTAT
16
DNC
17
RESETN
18
19
AVDD
20
AVDD
21
AVDD
Connect Thermal Pad to AVSS
D4
56
38
DNC
37
DNC
36
D12
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
DNC
29
DNC
30
DNC
31
D14
32
OVDD
33
DNC
34
DNC
35
DNC
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
1, 2, 17, 28, 29, 30, 33, 34,
35, 37, 38, 39, 41, 42, 43,
47, 49, 50, 51, 53, 54, 55,
57, 58, 59, 63
6, 13, 19, 20, 21, 70, 71, 72
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
CMOS PIN NAME
DNC
Do Not Connect
CMOS PIN FUNCTION
AVDD
AVSS
OVDD
OVSS
NAPSLP
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
4
FN7574.2
December 10, 2012
ISLA216P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
4
8, 9
10, 11
15
16
18
22, 23
24, 25
31
36
40
44
46
48
52
56
60
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VCM
VINN
VINP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D14
D12
D10
D8
RLVDS
CLKOUT
D6
D4
D2
D0
SDO
CSB
SCLK
SDIO
AVSS
Common Mode Output
Analog Input Negative
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
DDR Logical Bits 14, 15
DDR Logical Bits 12, 13
DDR Logical Bits 10, 11
DDR Logical Bits 8, 9
LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)
CMOS Clock Output
DDR Logical Bits 6, 7
DDR Logical Bits 4, 5
DDR Logical Bits 2, 3
DDR Logical Bits 0, 1
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
(Continued)
CMOS PIN FUNCTION
Ordering Information
PART NUMBER
(Notes 1, 2)
ISLA216P13IRZ
ISLA216P20IRZ
ISLA216P25IRZ
Coming Soon
ISLA216P13IR1Z
Coming Soon
ISLA216P20IR1Z
Coming Soon
ISLA216P25IR1Z
ISLA216IR72EV1Z
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for
ISLA216P.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISLA216P13 IRZ
ISLA216P20 IRZ
ISLA216P25 IRZ
ISLA216P13 IR1Z
ISLA216P20 IR1Z
ISLA216P25 IR1Z
Evaluation Board (72 pin QFN ADC)
TEMP. RANGE
(°C)
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PACKAGE
(Pb-free)
72 Ld QFN
72 Ld QFN
72 Ld QFN
48 Ld QFN
48 Ld QFN
48 Ld QFN
PKG.
DWG. #
L72.10x10E
L72.10x10E
L72.10x10E
TBD
TBD
TBD
5
FN7574.2
December 10, 2012