PH9930L
N-channel TrenchMOS logic level FET
Rev. 01 — 23 August 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I
Logic level threshold
I
Optimized for use in DC-to-DC
converters
I
100 % R
G
tested
I
Lead-free package
I
Very low switching and conduction
losses
I
100 % ruggedness tested
1.3 Applications
I
DC-to-DC converters
I
Voltage regulators
I
Switched-mode power supplies
I
PC motherboards
1.4 Quick reference data
I
V
DS
≤
30 V
I
R
DSon
≤
9.9 mΩ
I
I
D
≤
63 A
I
Q
GD
= 3.2 nC (typ)
2. Pinning information
Table 1.
Pin
1, 2, 3
4
mb
Pinning
Description
source (S)
gate (G)
mounting base; connected to drain (D)
mb
D
Simplified outline
Symbol
G
mbb076
S
1 2 3 4
SOT669 (LFPAK)
NXP Semiconductors
PH9930L
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
PH9930L
LFPAK
Description
plastic single-ended surface-mounted package (lfpak); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 33 A;
t
p
= 0.08 ms; V
DS
≤
30 V; R
GS
= 50
Ω;
V
GS
= 10 V; starting at T
j
= 25
°C
T
mb
= 25
°C;
V
GS
= 10 V; see
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V; see
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
see
Figure 3
T
mb
= 25
°C;
see
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
30
30
±20
63
39
214
62.5
+150
+150
52
208
53
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
PH9930L_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 August 2007
2 of 12
NXP Semiconductors
PH9930L
N-channel TrenchMOS logic level FET
120
P
der
(%)
80
003aab937
120
I
der
(%)
80
003aab757
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
j
(°C)
200
P
tot
P
der
=
-----------------------
×
100
%
-
P
tot
(
25°C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
I
D
I
der
=
-------------------
×
100
%
-
I
D
(
25°C
)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab730
t
p
=10
µs
100
µs
1 ms
10
10 ms
100 ms
1
10
−1
10
−1
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH9930L_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 August 2007
3 of 12
NXP Semiconductors
PH9930L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
R
th(j-mb)
Thermal characteristics
Conditions
Min
-
Typ
-
Max
2
Unit
K/W
thermal resistance from junction to mounting base see
Figure 4
Symbol Parameter
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
−1
0.05
0.02
single pulse
t
p
P
003aab731
δ
=
t
p
T
t
T
10
−2
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH9930L_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 August 2007
4 of 12
NXP Semiconductors
PH9930L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain leakage current
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
G
R
DSon
gate leakage current
gate resistance
drain-source on-state
resistance
V
GS
=
±16
V; V
DS
= 0 V
f = 1 MHz
V
GS
= 10 V; I
D
= 25 A; see
Figure 6
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 4.5 V; I
D
= 25 A; see
Figure 6
and
8
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GS1
Q
GS2
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
C
iss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
pre-V
GS(th)
gate-source charge
post-V
GS(th)
gate-source charge
gate-drain charge
gate-source plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
input capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 25 A; V
GS
= 0 V; see
Figure 13
I
S
= 20 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
GS
= 0 V; V
DS
= 0 V; f = 1 MHz
V
DS
= 12 V; R
L
= 0.5
Ω;
V
GS
= 4.5 V;
R
G
= 5.6
Ω
V
GS
= 0 V; V
DS
= 12 V; f = 1 MHz;
see
Figure 14
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V;
see
Figure 11
and
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13.3
4.8
3.0
1.8
3.2
2.72
1565
355
186
1839
20
41
15
25
0.89
43
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.16
-
-
nC
nC
nC
nC
nC
V
pF
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
7.2
11.9
10.5
9.9
15.8
13.5
mΩ
mΩ
mΩ
-
-
-
-
-
-
-
0.56
1
100
100
-
µA
µA
nA
Ω
1.3
0.8
-
1.7
-
-
2.15
-
2.6
V
V
V
30
27
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
PH9930L_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 August 2007
5 of 12
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