Product Brief
LLP
Link Layer Processor
F e at u r e s
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Overview
channels (transmit and receive, 56 kbits/s to
2.048 Mbits/s data rate per HDLC channel).
— Up to 128 PPP channels on any of up to 84
links, 84 ML PPP bundles, bundle sizes from
1-128 PPP channels.
— ML/MC/PPP support for up to 16 classes.
— Simultaneous processing for various packet
types: generic, PPP, ML/PPP, and ML/MC/PPP.
—Packet size up to 9600 bytes.
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Line interfaces:
— Up to 155 Mbits/s bidirectional
bandwidth through channelized
OC-3/STM-1:
• Up to three NSMI ports (51.84 Mbits/s
each) supporting up to 84 DS1/J1 links
or 63 E1 links.
— Supports up to 16 LIU ports with
internal framer.
— Four synchronous CHI ports for direct
TDM interface to time-slot interchanger
(TSI) devices.
The Link Layer Processor (LLP) offers a
highly integrated solution for multiservice
applications such as wireline access network
and 2.5G/3G wireless access applications. The
full bidirectional data bandwidth of the LLP can
be used entirely by a single protocol path or
can be simultaneously partitioned among the
three protocol paths, allowing migration from
circuit switching (TDM) to cell switching (ATM)
to packet switching (IP) on a common platform.
The LLP device supports multichannel ATM
transmission convergence (TC), inverse
multiplexing for ATM (IMA), ATM adaptation
layer type 1 segmentation and reassembly
(AAL1 SAR), multichannel high-level data
link control (HDLC), and multilink/multiclass
point-to-point protocol (ML/MC/PPP) data-link
layer functions. These protocols are processed
between DS1/E1/J1 links and industry standard
system interfaces (SPI-3, POS-PHY™ Level 2 or
UTOPIA-2).
All device features described in this product
brief are fully accessible through an LSI
supplied software package.
Subrate HDLC processing:
— Insertion and extraction for up to 64 subrate
(8 kbits/s to 64 kbits/s rate) HDLC channels.
Frame relay support:
— The LLP provides up to 672 HDLC terminations.
Transcoder rate adapter unit (TRAU) frame
support:
— Up to 940 TRAU channels with inband
messaging.
— Supports mappings of full-rate (FR), half-rate
(HR), and adaptive multirate (AMR HR) speech
into TRAU frames.
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8-bit SPI-3 (system packet interface Level 3),
8-bit/16-bit UTOPIA Level 2, or 8-bit/16-bit
POS-PHY Level 2, multi-PHY slave system
interface.
Embedded shared RAM for storage of
payload and control structures with
optional 16-bit DDR SDRAM interface for
external memory expansion.
Fractional DS1/J1/E1 logical channel
mapping to each of the three protocol
processing paths.
Line side NxDS0 cross connect via AAL0/1
ATM protocol processing for TC/IMA:
— Support for any combination of up to 84
IMA groups or UNI links with fractional
support.
— From 1 to 32 links per IMA group.
AAL1 SAR processing:
— Up to 672 virtual circuits (VCs).
— Supports both structured data transfer
(SDT mode) and unstructured data
transfer (UDT) modes.
— Clock recovery for adaptive clocking
scheme.
— Channel associated signaling (SDT
mode).
— Partial fill of ATM cells (SDT mode).
ML/MC/PPP HDLC processing:
— HDLC framing and deframing for up to
672 HDLC
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516-pin PBGA package (31 mm x 31 mm).
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LLP Block Diagram
Applications
Media gateways, routers, RNCs, pseudo wire applications
Ordering Information
Below is the ordering information for one product in the LLP family. Please refer to the LLP Family
Selection Guide for details on other products available in this same family.
O r d e r i n g i n F O r m at i O n :
Device
LLP16084
Part Number
LLP1608421BL1-DB
L-LLP1608421BL1-DB
Comcode
711010275
711010276
Package
516 PBGAM1T
516 PBGAM1T
Note: Part numbers beginning with L- are RoHS compliant.
For more information and sales office locations, please visit the LSI web sites at:
lsi.com lsi.com/contacts
LSI Corporation and, LSI logo design The Communications Company, are trademarks or registered trademarks of LSI Corporation.
All other brand and product names may be trademarks of their respective companies. LSI Corporation reserves the right to make changes to any
products and services herein at any time without notice. LSI does not assume any responsibility or liability arising out of the application or use
of any product or service described herein, except as expressly agreed to in writing by LSI; nor does the purchase, lease, or use of a product or
service from LSI convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI or
of third parties.
Copyright ©2006 by LSI Corporation. All rights reserved.
August 3, 2006
PB05-027MPIC-1 (Replaces PB05-027MPIC)
Embedded System
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