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FTS128K32N-35H2B

Description
Standard SRAM, 128KX32, 35ns, CMOS, CQFP68, CERAMIC, QFP-68
Categorystorage    storage   
File Size748KB,9 Pages
ManufacturerForce Technologies Ltd.
Download Datasheet Parametric View All

FTS128K32N-35H2B Overview

Standard SRAM, 128KX32, 35ns, CMOS, CQFP68, CERAMIC, QFP-68

FTS128K32N-35H2B Parametric

Parameter NameAttribute value
MakerForce Technologies Ltd.
Parts packaging codeQFP
package instructionQFP,
Contacts68
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time35 ns
JESD-30 codeS-CQFP-G68
JESD-609 codee4
length22.36 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width32
Number of functions1
Number of terminals68
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQFP
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height3.51 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationQUAD
width22.36 mm
Base Number Matches1
FTS128K32-XXX
128Kx32 SRAM MODULE
Features
Packaging
• 66 pin, PGA Type
(H1),
1.075" square, Hermetic
Ceramic HIP (Package
A100)
• 68 lead, 22.4mm CQFP (H2), 3.56mm (0.140"),
(Package
C100)
• 68 lead, 22.4mm (0.880") square, CQFP (H3),
5.08mm (0.200") high, (Package
B100)
Organised as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Commercial, Industrial and Military Temperature
Ranges
5 Volt Power Supply
Access Times of 15, 17, 20, 25, 35, 45, 55ns
MIL-STD-883
M5004
Available
Low Power CMOS
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
FIGURE 1 – PIN CONFIGURATION FOR
FTS128K32N-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
WE#1 CS#1
WE#2 CS#2
WE#3 CS#3
WE#4 CS#4
Pin Description
56
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
I/O
23
I/O
22
I/O
21
OE#
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O
20
66
I/O 0-7
I/O 8-15
I/O 16-23
I/O 24-31
1
Sep 2006
Rev 1
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