74ACTQ74 Quiet Series Dual D-Type
March 1993
Revised November 1999
74ACTQ74
Quiet Series Dual D-Type
Positive Edge-Triggered Flip-Flop
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q) out-
puts. Information at the input is transferred to the outputs
on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive-going
pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next
rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes
both Q and Q HIGH
Features
s
I
CC
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
4 kV minimum ESD immunity
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACTQ74SC
74ACTQ74SJ
74ACTQ74PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010920
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74ACTQ74
Truth Table
(Each Half)
Inputs
S
D
L
H
L
H
H
H
C
D
H
L
L
H
H
H
CP
X
X
D
X
X
X
H
L
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
Logic Symbols
L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
=
Previous Q(Q) before LOW-to-HIGH Transition of Clock
IEEE/IEC
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACTQ74
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or Sink Current
Junction Temperature (T
J
) PDIP
±
50 mA
−65°C
to
+150°C
±
300 mA
140°C
±
50 mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT circuits outside databook specifi-
cations.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 2)
Maximum Quiescent Supply Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
2.0
1.5
−1.2
2.2
0.8
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
±
0.5
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
±
5.0
1.5
75
−75
20.0
V
µA
µA
mA
mA
mA
µA
V
V
V
V
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
I
OH
=
−24
mA
I
OH
=
−24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
(Note 4)(Note 6)
Units
Conditions
V
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
PDIP package.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6:
Max number of data inputs (n) switching. (n
−
1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1 MHz.
3
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74ACTQ74
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 7)
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
OSLH
t
OSHL
Maximum Clock Frequency
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
Propagation Delay
CP
n
to Q
n
or Q
n
Output to Output
Skew (Note 8)
5.0
5.0
Min
145
3.0
T
A
= +25°C
C
L
=
50 pF
Typ
200
7.0
8.5
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
125
3.0
9.0
Max
MHz
ns
Units
5.0
5.0
3.0
6.5
0.5
8.0
1.0
3.0
8.6
1.0
ns
ns
Note 7:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW
-
to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 9)
t
S
t
H
t
W
t
REC
Setup Time, HIGH or LOW
D
n
to CP
n
Hold Time, HIGH or LOW
D
n
to CP
n
CP
n
or C
Dn
or S
Dn
Pulse Width
Recovery Time
C
Dn
or S
Dn
to CP
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Typ
1.0
−0.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
3.0
1.5
3.0
1.5
ns
ns
Units
5.0
5.0
5.0
3.0
−2.5
4.0
4.0
ns
5.0
1.5
1.5
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
60.0
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
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4
74ACTQ74
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case transition for active and enable.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
OHV
and V
OLP
are measured with respect to ground reference.
Input pulses have the following characteristics: f
=
1 MHz, t
r
=
3 ns,
t
f
=
3 ns, skew
<
150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
5
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