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74LVX273MX

Description
IC D-type pos trg sngl 20soic
Categorylogic    logic   
File Size91KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX273MX Overview

IC D-type pos trg sngl 20soic

74LVX273MX Parametric

Parameter NameAttribute value
Brand NameFairchild Semiconductor
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP20,.4
Contacts20
Manufacturer packaging code20LD, SOIC, JEDEC MS013, .300\", WIDE BODY
Reach Compliance Codecompliant
ECCN codeEAR99
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup50000000 Hz
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup16.5 ns
propagation delay (tpd)24 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.5 mm
minfmax80 MHz
Base Number Matches1
74LVX273 Low Voltage Octal D-Type Flip-Flop
June 1993
Revised April 2005
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX273M
74LVX273SJ
74LVX273MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Description
Reset (Clear)
Load '1'
Load '0'
H HIGH Voltage Level
L LOW Voltage Level
Operating Mode
MR
L
H
H
Inputs
CP
D
n
X
H
L
Outputs
Q
n
L
H
L



X
X
Immaterial
LOW-to-HIGH Transition
© 2005 Fairchild Semiconductor Corporation
DS011614
www.fairchildsemi.com

74LVX273MX Related Products

74LVX273MX 74LVX273SJX
Description IC D-type pos trg sngl 20soic IC D-type pos trg sngl 20sop
Brand Name Fairchild Semiconductor Fairchild Semiconductor
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker Fairchild Fairchild
Parts packaging code SOIC SOP
package instruction SOP, SOP20,.4 SOP, SOP20,.3
Contacts 20 20
Manufacturer packaging code 20LD, SOIC, JEDEC MS013, .300\", WIDE BODY 20LD,SOP,EIAJ TYPE II, 5.3MM WIDE
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
series LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e3
length 12.8 mm 12.6 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP
Maximum Frequency@Nom-Sup 50000000 Hz 50000000 Hz
MaximumI(ol) 0.004 A 0.004 A
Humidity sensitivity level 1 1
Number of digits 8 8
Number of functions 1 1
Number of terminals 20 20
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output polarity TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Encapsulate equivalent code SOP20,.4 SOP20,.3
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
method of packing TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 16.5 ns 16.5 ns
propagation delay (tpd) 24 ns 24 ns
Certification status Not Qualified Not Qualified
Maximum seat height 2.65 mm 2.1 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V 2.7 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE
width 7.5 mm 5.3 mm
minfmax 80 MHz 80 MHz
Base Number Matches 1 1

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