Freescale Semiconductor
Data Sheet:
Document Number: MSC8122
Rev. 16, 12/2008
MSC8122
FC PBGA–431
20 mm
×
20 mm
Quad Digital Signal
Processor
• Four StarCore™ SC140 DSP extended cores, each with an SC140
DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte
total), 16 way 16 Kbyte instruction cache (ICache), four-entry
write buffer, external cache support, programmable interrupt
controller (PIC), local interrupt controller (LIC), and low-power
Wait and Stop processing modes.
• 475 Kbyte M2 memory for critical data and temporary data
buffering.
• 4 Kbyte boot ROM.
• M2-accessible multi-core MQBus connecting the M2 memory
with all four cores, operating at the core frequency, with data bus
access of up to 128-bit reads and up to 64-bit writes, central
efficient round-robin arbiter for core access to the bus, and atomic
operation control of M2 memory access by the cores and the local
bus.
• Internal PLL configured are reset by configuration signal values.
• 60x-compatible system bus with 64 or 32 bit data and 32-bit
address bus, support for multi-master designs, four-beat burst
transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8
bits controlled by the internal memory controller,.access to
external memory or peripherals, access by an external host to
internal resources, slave support with direct access to internal
resources including M1 and M2 memories, and on-device
arbitration for up to four master devices.
• Direct slave interface (DSI) using a 32/64-bit slave host interface
with 21–25 bit addressing and 32/64-bit data transfers, direct
access by an external host to internal and external resources,
synchronous or asynchronous accesses with burst capability in
synchronous mode, dual or single strobe mode, write and read
buffers to improve host bandwidth, byte enable signals for
1/2/4/8-byte write granularity, sliding window mode for access
using a reduced number of address pins, chip ID decoding to
allow one CS signal to control multiple DSPs, broadcast mode to
write to multiple DSPs, and big-endian/little-endian/munged
support.
• Three mode signal multiplexing: 64-bit DSI and 32-bit system
bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit
system bus.
• Flexible memory controller with three UPMs, a GPCM, a
page-mode SDRAM machine, glueless interface to a variety of
memories and devices, byte enables for 64- or 32-bit bus widths,
•
8 memory banks for external memories, and 2 memory banks for
IPBus peripherals and internal memories.
Multi-channel DMA controller with 16 time-multiplexed single
channels, up to four external peripherals, DONE or DRACK
protocol for two external peripherals,.service for up to 16 internal
requests from up to 8 internal FIFOs per channel, FIFO generated
watermarks and hungry requests, priority-based
time-multiplexing between channels using 16 internal priority
levels or round-robin time-multiplexing between channels,
flexible channel configuration with connection to local bus or
system bus, and flyby transfer support that bypasses the FIFO.
Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 128 Mbps data rate for all channels, with glueless interface
to E1 or T1 framers, and can interface with H-MVIP/H.110
devices, TSI, and codecs such as AC-97.
Ethernet controller with support for 10/100 Mbps MII/RMII/SMII
including full- and half-duplex operation, full-duplex flow
controls, out-of-sequence transmit queues, programmable
maximum frame length including jumbo frames and VLAN tags
and priority, retransmission after collision, CRC generation and
verification of inbound/outbound packets, address recognition
(including exact match, broadcast address, individual hash check,
group hash check, and promiscuous mode), pattern matching,
insertion with expansion or replacement for transmit frames,
VLAN tag insertion, RMON statistics, local bus master DMA for
descriptor fetching and buffer access, and optional multiplexing
with GPIO (MII/RMII/SMII) or DSI/system bus signals lines
(MII/RMII).
UART with full-duplex operation up to 6.25 Mbps.
Up to 32 general-purpose input/output (GPIO) ports.
I
2
C interface that allows booting from EEPROM devices.
Two timer modules, each with sixteen configurable 16-bit timers.
Eight programmable hardware semaphores.
Global interrupt controller (GIC) with interrupt consolidation and
routing to INT_OUT, NMI_OUT, and the cores; thirty-two virtual
maskable interrupts (8 per core) and four virtual NMI (one per
core) that can be generated by a simple write access.
Optional booting external memory, external host, UART, TDM,
or I
2
C.
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© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .15
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .39
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .39
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .40
3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .41
3.4 External SDRAM Selection . . . . . . . . . . . . . . . . . . . . . .42
3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .43
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 10.Internal Tick Spacing for Memory Controller Signals. . .
Figure 11.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . .
Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15.Asynchronous Single- and Dual-Strobe Modes Write
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16.Asynchronous Broadcast Write Timing Diagram . . . . . .
Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . .
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . .
Figure 24.MII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25.RMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . .
Figure 26.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . .
Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . .
Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . .
Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . .
Figure 32.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . .
Figure 34.V
CCSYN
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35.MSC8122 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
25
26
27
29
30
30
31
32
32
33
33
34
34
35
35
36
37
37
38
38
39
39
40
41
44
3
4
5
6
7
List of Figures
MSC8122 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
StarCore SC140 DSP Extended Core Block Diagram . . 3
MSC8122 Package, Top View . . . . . . . . . . . . . . . . . . . . 5
MSC8122 Package, Bottom View . . . . . . . . . . . . . . . . . . 6
Overshoot/Undershoot Voltage for V
IH
and V
IL
. . . . . . . 16
Start-Up Sequence: V
DD
and V
DDH
Raised Together . . 17
Start-Up Sequence: V
DD
Raised Before V
DDH
with CLKIN
Started with V
DDH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Power-Up Sequence for V
DDH
and V
DD
/V
CCSYN
. . . . . 18
Figure 9. Timing Diagram for a Reset Configuration Write . . . . . 21
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
2
Freescale Semiconductor
Analogue and Mixed Signal
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