K7A163601A
K7A163201A
K7A161801A
512Kx36/32 & 1Mx18 Synchronous SRAM
16Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
6.5/7.5/8.5ns
138MHz
250/225/200/167/138MHz
C
(Commercial
250/225/200/167/138MHz
Temperature
6.5/7.5/8.5ns
Q : 100TQFP
Range)
138MHz
H : 119BGA
F : 165FBGA
250/225/200/167/138MHz
I
250/225/200/167/138MHz
(Industrial
Temperature
6.5/7.5/8.5ns
Range)
138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
PKG
Temp
K7B161825A-Q(H/F)C(I)65/75/85
1Mx18
K7A161880A-QC(I)14
SB
SPB(2E1D)
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
K7A161800A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)
K7A161801A-QC(I)25/22/20/16/14
K7B163225A-QC(I)65/75/85
512Kx32 K7A163280A-QC(I)14
K7A163200A-QC(I)25/22/20/16/14
K7A163201A-QC(I)25/22/20/16/14
K7B163625A-Q(H/F)C(I)65/75/85
512Kx36
K7A163680A-QC(I)14
SPB(2E2D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SB
SPB(2E1D)
K7A163600A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)
K7A163601A-QC(I)25/22/20/16/14
SPB(2E2D)
-2-
May 2002
Rev 2.0
K7A163601A
K7A163201A
K7A161801A
512Kx36/32 & 1Mx18 Synchronous SRAM
512Kx36/32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 2cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A163601A , K7A163201A and K7A161801A are
18,874,368-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pentium
and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A163601A, K7A163201A and K7A161801A are fabri-
cated using SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.6
2.6
-22
4.4
2.8
2.8
-20
5.0
3.1
3.1
-16
6.0
3.5
3.5
-14
7.2
4.0
4.0
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
A′
0
~A′
1
512Kx36/32 , 1Mx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
-3-
May 2002
Rev 2.0
京公网安备 11010802033920号
EEWORLD
