MSC8103 Features .................................................................................................................................................................................... iii
Power Signals ........................................................................................................................................................................ 1-4
Reset, Configuration, and EOnCE Event Signals.................................................................................................................. 1-5
System Bus, HDI16, and Interrupt Signals............................................................................................................................ 1-6
JTAG Test Access Port Signals............................................................................................................................................ 1-36
Absolute Maximum Ratings .................................................................................................................................................. 2-1
DC Electrical Characteristics................................................................................................................................................. 2-3
AC Timings............................................................................................................................................................................ 2-7
Power Considerations ............................................................................................................................................................ 4-2
Ordering and Contact Information ...............................................................................................................................Back Cover
Data Sheet Conventions
pin and pin-
out
Although the device package does not have pins, the term pins and pin-out are used for
convenience and indicate specific signal locations within the ball-grid array.
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the
RESET
pin is active
when low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted”
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples:
Signal/Symbol
Logic State
Signal State
Voltage
PIN
True
Asserted
V
IL
/V
OL
PIN
False
Deasserted
V
IH
/V
OH
PIN
True
Asserted
V
IH
/V
OH
PIN
False
Deasserted
V
IL
/V
OL
Note:
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
MSC8103 Network Digital Signal Processor, Rev. 12
ii
Freescale Semiconductor
MSC8103 Features
•
SC140 core
— Architecture optimized for efficient C/C++ code compilation
— Four 16-bit ALUs and two 32-bit AGUs
— 1200 DSP MMACS running at 300 MHz
— Very low power dissipation
— Variable-length execution set (VLES) execution model
— JTAG/Enhanced OnCE debug port
Communications processor module (CPM)
— Programmable protocol machine using a 32-bit RISC engine
— 155 Mbps ATM interface (including AAL 0/1/2/5)
— 10/100 Mbit Ethernet interface
— Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
— HDLC support up to T3 rates, or 256 channels
64- or 32-bit wide bus interface
— Support for bursts for high efficiency
— Glueless interface to 60x-compatible bus systems
— Multi-master support
Programmable memory controller
— Control for up to eight banks of external memory
— User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM,
EPROM, and Flash memory) and other user-definable peripherals
— Dedicated pipelined SDRAM memory interface
Large internal SRAM
— 256K 16-bit words (512 KB)
— Unified program and data space configurable by the application
— Word and byte addressable
DMA controller
— 16 DMA channels, FIFO based, with burst capabilities
— Sophisticated addressing capabilities
Small foot print package
— 17 mm
×
17 mm lidded FC-PBGA package with lead-bearing or lead-free spheres
Very low power consumption
— Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
Enhanced 16-bit parallel host interface (HDI16)
— Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
Phase-lock loops (PLLs)
— System PLL
— CPM DPLLs (SCC and SCM)
Process technology
— 0.13 micron copper interconnect process technology
•
•
•
•
•
•
•
•
•
•
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
iii
Target Applications
The MSC8103 targets applications requiring very high performance, very large amounts of internal memory, and
such networking capabilities as:
•
•
•
•
Third-generation wideband wireless infrastructure systems
Packet Telephony systems
Multi-channel modem banks
Multi-channel xDSL
Product Documentation
The documents listed in
Table 1
are required for a complete description of the MSC8103 and are necessary to
design properly with the part. Documentation is available from the following sources (see back cover for details):
•
•
•
•
A local Freescale distributor
A Freescale Semiconductor sales office
A Freescale Semiconductor Literature Distribution Center
The world wide web (WWW)
Table 1.
MSC8103 Documentation
Name
MSC8103
Technical Data
MSC8101 User’s Guide
Description
MSC8103 features list and physical, electrical, timing, and package
specifications
Detailed functional description of the MSC8101 memory
configuration, operation, and register programming. All details apply
to the MSC8103.
Detailed description of the MSC8103 processor core and instruction
set
Detailed description of the SC140 family processor core and
instruction set
Documents describing specific applications or optimized device
operation including code examples
Order Number
MSC8103/D
MSC8101UG/D
MSC8103 Reference Manual
SC140 DSP Core Reference Manual
Application Notes
MSC8103RM/D
MNSC140CORE/D
See the MSC8103 product
website
MSC8103 Network Digital Signal Processor, Rev. 12
iv
Freescale Semiconductor
Signals/Connections
1
The MSC8103 external signals are organized into functional groups, as shown in
Table 1-1, Figure 1-1,
and
Figure 1-2. Table 1-1
lists the functional groups, states the number of signal connections in each group, and
references the table that gives details on multiplexed signals within each group.
Figure 1-1
shows MSC8103
external signals organized by function.
Figure 1-2
indicates how the parallel input/output (I/O) ports signals are
multiplexed. Because the parallel I/O design supported by the MSC8103 communications processor module
(CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered
sequentially.
Table 1-1.
Functional Group
Power (V
CC
, V
DD
, and GND)
Clock
Reset, configuration, and EOnCE
System bus, HDI16, and interrupts
Memory controller
CPM input/output parallel ports
Port A
Port B
Port C
Port D
JTAG test access port (TAP)
Reserved (denotes connections that are always reserved)
京公网安备 11010802033920号
EEWORLD
