KMSC8122TVT6400 datasheet, PDF

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KMSC8122TVT6400: Descriptiondsp 16bit quad core 431-fcpbga; Categorysemiconductor The embedded processor and controller; File Size1MB，88 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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KMSC8122TVT6400 Overview

dsp 16bit quad core 431-fcpbga

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Freescale Semiconductor

Technical Data

MSC8122

Rev. 12, 4/2006

MSC8122

Quad Core 16-Bit Digital Signal Processor

The raw processing power of

this highly integrated system-

on- a-chip device will enable

developers to create next-

generation networking

products that offer

tremendous channel

densities, while maintaining

system flexibility, scalability,

and upgradeability. The

MSC8122 is offered in three

core speed levels: 300, 400,

and 500 MHz.

What’s New?

Rev. 12

includes the following:

MII/RMII/SMII

• Chapter 2

updates

Figure 2-11

for reset timing.

SC140

Extended Core

MQBus

SC140

Extended Core

128

SQBus

SC140

Extended Core

SC140

Extended Core

128

IP Master

32 Timers

Local Bus

Boot

ROM

RAM

Memory

Controller

UART

4 TDMs

RS-232

PLL/Clock

PLL

IPBus

GPIO

GIC

8 Hardware

Semaphores

Ethernet

GPIO Pins

Interrupts

JTAG Port

JTAG

System

Interface

Internal Local Bus

SIU

Registers

DMA

Bridge

Direct

Slave

Interface

(DSI)

Memory

Controller

DSI Port

32/64

System Bus

32/64

Internal System Bus

Figure 1.

MSC8122 Block Diagram

The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232

serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a

flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended

cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.

Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.

The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless

transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers

enhanced performance while maintaining low power dissipation and greatly reducing system cost.

Table of Contents

Features...............................................................................................................................................................iv

Product Documentation ......................................................................................................................................ix

Chapter 1

Signals/Connections

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

Power Signals ...................................................................................................................................................1-3

Clock Signals ....................................................................................................................................................1-3

Reset and Configuration Signals.......................................................................................................................1-3

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4

Memory Controller Signals ............................................................................................................................1-14

GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16

Dedicated Ethernet Signals.............................................................................................................................1-23

EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24

Reserved Signals.............................................................................................................................................1-24

Maximum Ratings.............................................................................................................................................2-1

Recommended Operating Conditions...............................................................................................................2-2

Thermal Characteristics ....................................................................................................................................2-3

DC Electrical Characteristics............................................................................................................................2-3

AC Timings.......................................................................................................................................................2-4

Package Description .........................................................................................................................................3-1

MSC8122 Package Mechanical Drawing .......................................................................................................3-20

Chapter 2

Specifications

2.1

2.2

2.3

2.4

2.5

Chapter 3

Packaging

3.1

3.2

Chapter 4

Design Considerations

4.1

4.2

4.3

4.4

4.5

Start-up Sequencing Recommendations ...........................................................................................................4-1

Power Supply Design Considerations...............................................................................................................4-1

Connectivity Guidelines ...................................................................................................................................4-3

External SDRAM Selection..............................................................................................................................4-4

Thermal Considerations....................................................................................................................................4-5

Data Sheet Conventions

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the

RESET

pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note:

Values for

, and

are defined by individual product specifications.

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor

Features

Feature

Description

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode

SDRAM machine.

• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable

peripherals.

• Byte enables for either 64-bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

— 32-bit address decoding with programmable mask.

— Variable block sizes (32 KB to 4 GB).

— Selectable memory controller machine.

— Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even

parity for single accesses.

— Write-protection capability.

— Control signal generation machine selection on a per-bank basis.

— Support for internal or external masters on the system bus.

— Data buffer controls activated on a per-bank basis.

— Atomic operation.

— RMW data parity check (on system bus only).

— Extensive external memory-controller/bus-slave support.

— Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus

only).

— Data pipeline to reduce data set-up time for synchronous devices.

•

Multi-Channel DMA

Controller

16 time-multiplexed unidirectional channels.

Services up to four external peripherals.

Supports DONE or DRACK protocol on two external peripherals.

Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

— A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

— A hungry request to indicate that the FIFO can accept more data.

Priority-based time-multiplexing between channels using 16 internal priority levels.

Round-robin time-multiplexing between channels.

A flexible channel configuration:

— All channels support all features.

— All channels connect to the system bus or local bus.

Flyby transfers in which a single data access is transferred directly from the source to the destination without

using a DMA FIFO.

Memory Controller

•

Time-Division

Multiplexing (TDM)

Up to four independent TDM modules, each with the following features:

• Optional operating configurations:

— Totally independent receive and transmit channels, each having one data line, one clock line, and one frame

sync line.

— Four data lines with one clock and one frame sync shared among the transmit and receive lines.

• Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS.

• Hardware A-law/µ-law conversion.

• Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used,

15.63 MHz if four data lines are used).

• Up to 256 channels.

• Up to 16 MB per channel buffer (granularity 8 bytes), where A/µ law buffer size is double (granularity 16 byte).

• Receive buffers share one global write offset pointer that is written to the same offset relative to their start

address.

• Transmit buffers share one global read offset pointer that is read from the same offset relative to their start

address.

• All channels share the same word size.

• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can

be used, for example, to implement double buffering.

• Each channel can be programmed to be active or inactive.

• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

• The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge

of the clock.

• Frame sync can be programmed as active low or active high.

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

• MSB or LSB first support.

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor

KMSC8122TVT6400 Related Products

	KMSC8122TVT6400	KMSC8122MP8000	KMSC8122TVT4800V	KMSC8122TMP4800V	KMSC8122TMP6400	KMSC8122TMP6400V	KMSC8122TVT6400V	KMSC8122VT8000
Description	dsp 16bit quad core 431-fcpbga	dsp 16bit quad 500mhz 431-fcpbga	dsp 16bit quad 300mhz 431-fcpbga	dsp 16bit quad 300mhz 431-fcpbga	dsp 16bit quad core 431-fcpbga	dsp 16bit quad core 431-fcpbga	dsp 16bit quad core 431-fcpbga	dsp 16bit quad 500mhz 431-fcpbga

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