IDT71V3557SA75BGGI datasheet, PDF

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IDT71V3557SA75BGGI: DescriptionIC sram 4.5mbit 7.5ns 119bga; Categorystorage; File Size997KB，28 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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IDT71V3557SA75BGGI Overview

IC sram 4.5mbit 7.5ns 119bga

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128K x 36, 256K x 18,

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

IDT71V3557S

IDT71V3559S

IDT71V3557SA

IDT71V3559SA

Features

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates

the need to control

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V

DDQ

)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

Description

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and on the next clock cycle the associated data cycle occurs, be

it read or write.

The IDT71V3557/59 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three is not asserted

when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

selected or a write is initiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

Static

5282 tbl 01

Pin Description Summary

-A

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

, CE

CEN

CLK

ADV/

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

DECEMBER 2005

DSC-5282/08

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