Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
4875 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
I made a handwriting input method. After writing, the stylus traces are left on the desktop. I want to erase the last trace when I write next time. I want to know what API can be used to achieve this ...
Maychang's Interesting Electronic Technology History Lecture 2: The Early History of Switching Power Supplies (I) and (II) After studying analog circuits for more than ten years, I recently realized t...
Hey guys , I'm a novice, I want to ask about a thyristor current limiting circuit problem. I don't know how to determine the resistance of the circuit ? I hope you guys can help me analyze it.The func...
Design a traffic light simulation control system using 8051 single-chip microcomputer, with a crystal oscillator of 12MHz. Specific requirements: Under normal circumstances, lanes A and B (lanes A and...
1. About FPU transplantation As long as the chip has FPU function, the use of FPU is generally enabled by default. You can also select it in the Options tab; 2. About the transplantation of DSP li...[Details]
On the eve of Qingming Festival, the trade friction between China and the United States is on the rise. Let's follow the automotive electronics editor to learn more about the relevant content. Ba...[Details]
On April 16, the U.S. Department of Commerce announced that it would ban U.S. companies from selling parts, goods, software, and technology to
ZTE
for seven years, until March 13, 2025.
Th...[Details]
The parking assistance system is an important application of the active anti-collision system of automobiles in low-speed and complex urban environments, and is also a specific embodiment of the inte...[Details]
The pins of stm32 have two uses: GPIO (general purpose io) and AFIO (alternate function io) For some pins (depending on the chip), neither of these two uses exists. For example, in 64-pin products, O...[Details]
I have encountered many problems when tinkering with LD driver recently. I will record them one by one below. Otherwise, who will remember who in five hundred years? 1. Configuration issues of multi-...[Details]
In the packaging process of a production line, every time the conveyor belt of the production line delivers a product to the packaging machine, the "SP" terminal outputs a pulse to the T1 terminal of...[Details]
Please help me analyze the clock cycles occupied by the following delay program. Seek to explain: DELAY: MOV R6, #13 DELAY1: MOV R5, #250 DELAY2: NOP DJNZ R5, DELAY2 DJNZ R6, DEL...[Details]
The record harmony method is as follows: Note: This method is compatible with the C32 compiler, not the XC32 compiler; 1. cmd opens the command window; 2. cd to the pic32-upgrader file where you inst...[Details]
Each I/O port of the AVR microcontroller corresponds to three registers: DDRx, PORTx and PINx, where DDRx is the data direction, i.e. input or output; PORTx is the state of the internal pull-up r...[Details]
Three multi-byte binary subtraction Subtract the binary unsigned number in 0x20,0x21 from the binary unsigned number in 0x22,0x23, and put the lower byte data in the lower address. Assume that the mi...[Details]
; ******************************************** ; Function : RS232 serial port sample program based on HT48R50A * ; MICroProcessor : HT48R50A-1/28SKDIP-A * ; Author: www.picavr.com * ; Crystal ...[Details]
The usage of 89S51 watchdog function is as follows: In the initialization of the program, write 01EH first and then write 0E1H to the watchdog register (WDTRST address is 0A6H). The watchdog can be...[Details]
Scientists have developed an
electronic skin
that allows users to manipulate virtual objects remotely
, which will further enhance the user's immersive virtual experience. Let's follow the ...[Details]
Embedded System
京公网安备 11010802033920号
EEWORLD
