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SY55852UKGTR

Description
55852 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO10, LEAD FREE, MSOP-10
Categorylogic    logic   
File Size51KB,7 Pages
ManufacturerMicrel ( Microchip )
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Parametric View All

SY55852UKGTR Overview

55852 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO10, LEAD FREE, MSOP-10

SY55852UKGTR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeMSOP
package instructionTSSOP,
Contacts10
Reach Compliance Codecompliant
series55852
JESD-30 codeS-PDSO-G10
JESD-609 codee4
length3 mm
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals10
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)0.4 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.7 V
Minimum supply voltage (Vsup)2.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
Trigger typePOSITIVE EDGE
width3 mm
minfmax2500 MHz
Base Number Matches1
Micrel, Inc.
D FLIP-FLOP
SuperLite™
SY55852U
SuperLite™
SY55852U
FEATURES
s
2.5GHz min. f
MAX
s
2.3V to 5.7V power supply
s
Single bit register memory
s
Synchronizes 1 bit of data to a clock
s
Optimized to work with SuperLite™ family
s
Fully differential
s
Accepts CML, PECL, LVPECL input logic levels
s
Source terminated CML outputs for fast edge rates
s
Available in a tiny 10-pin MSOP
SuperLite™
DESCRIPTION
The SY55852U is a flip-flop used to synchronize data
to a clock. Its differential output will reproduce and
remember the value on its input at the rising edge of the
clock. In addition, an asynchronous, level sensitive reset
is provided. For a synchonous reset, the SY55851U
AnyGate™ can be used.
SY55852U inputs can be terminated with a single
resistor between the true and complement pins of a given
input.
The SY55852U is a member of Micrel's SuperLite™
family of high-speed CML logic. This family features very
small packaging and 2.3V to 5.7V operation.
APPLICATIONS
s
High-speed logic
s
OC-48 communication systems
FUNCTIONAL BLOCK DIAGRAM
DATA
CLOCK
D
Q
OUT
R
RESET
SuperLite is a trademark of Micrel, Inc.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: November 2005
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