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Data Sheet
REC LE SUB 2346, ISL
N O T S SI B
I SL 2
PO
840,
X95
®
X9522
Laser Diode Control for Fiber Optic Modules
September 7, 2010
FN8208.2
Triple DCP, Dual Voltage Monitors
FEATURES
• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10kΩ
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin package
—TSSOP
DESCRIPTION
The X9522 combines three Digitally Controlled
Potentiometers (DCPs), and two programmable
voltage monitor inputs with software and hard-
ware indicators. All functions of the X9522 are
accessed by an industry standard 2-Wire serial
interface.
Two of the DCPs of the X9522 may be utilized to
control the bias and modulation currents of the
laser diode in a Fiber Optic module. The third DCP
may be used to set other various reference quanti-
ties, or as a coarse trim for one of the other two
DCPs.The programmable voltage monitors may be
used for monitoring various module alarm levels.
The features of the X9522 are ideally suited to sim-
plifying the design of fiber optic modules. The
integration of these functions into one package
significantly reduces board area, cost and
increases reliability of laser diode modules.
BLOCK DIAGRAM
R
H0
WIPER
COUNTER
REGISTER
R
W0
R
L0
8
WP
PROTECT LOGIC
6 - BIT
NONVOLATILE
MEMORY
R
H1
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
WIPER
COUNTER
REGISTER
R
W1
R
L1
CONSTAT
REGISTER
7 - BIT
NONVOLATILE
MEMORY
R
H2
WIPER
COUNTER
REGISTER
THRESHOLD
RESET LOGIC
R
W2
R
L2
2
8 - BIT
NONVOLATILE
MEMORY
V3
VTRIP
3
-
+
-
+
V3RO
V2
VTRIP
2
V2RO
Vcc / V1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9522
Ordering Information
PART NUMBER
X9522V20I-A
X9522V20I-B
X9522V20IZ-A (Note)
X9522V20IZ-B (Note)
PART MARKING
X9522VIA
X9522VIB
X9522VZIA
X9522VZIB
PRESET (FACTORY SHIPPED) V
TRIPx
THRESHOLD LEVELS (x = 2, 3)
Optimized for 3.3V system monitoring
Optimized for 5V system monitoring
Optimized for 3.3V system monitoring
Optimized for 5V system monitoring
TEMP RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8208.2
September 7, 2010
X9522
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W2
R
L2
V3
V3RO
NC
WP
SCL
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc / V1
NC
V2RO
V2
R
L0
R
W0
R
H0
R
H1
R
W1
R
L1
NOT TO SCALE
DETAILED DEVICE DESCRIPTION
The X9522 combines three Intersil Digitally Con-
trolled Potentiometer (DCP) devices, and two volt-
age monitors, in one package. These functions are
suited to the control, support, and monitoring of
various system parameters in fiber optic modules.
The combination of the X9522 functionality lowers
system cost, increases reliability, and reduces
board space requirements.
Two high resolution DCPs allow for the “set-and-
forget” adjustment of Laser Driver IC parameters
such as Laser Diode Bias and Modulation Cur-
rents. One lower resolution DCP may be used for
setting sundry system parameters such as maxi-
mum laser output power (for eye safety require-
ments).
The dual Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If
an input voltage exceeds it’s associated trip level,
a hardware output (V3RO, V2RO) are allowed to go
HIGH. If the input voltage becomes lower than it’s
associated trip level, the corresponding output is
driven LOW. A corresponding binary representa-
tion of the two monitor circuit outputs (V2RO and
V3RO) are also stored in latched, volatile (CON-
STAT) register bits. The status of these two moni-
tor outputs can be read out via the 2-wire serial
port.
Intersil’s unique circuits allow for all internal trip
voltages to be individually programmed with high
accuracy. This gives the designer great flexibility
in changing system parameters, either at the time
of manufacture, or in the field.
The device features a 2-Wire interface and soft-
ware protocol allowing operation on an I
2
C™ com-
patible serial bus.
3
FN8208.2
September 7, 2010
X9522
PIN ASSIGNMENT
Pin
1
2
3
4
Name
R
H2
R
w2
R
L2
V3
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH level. Connect
V3 to V
SS
when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
TRIP3
and goes LOW when V3 is less than V
TRIP3
. There is no delay circuitry on this pin. The V3RO
pin requires the use of an external “pull-up” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to
“1”), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the
wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an
internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re-
sistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition to a HIGH level. Connect
V2 to V
SS
when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
V
TRIP2
, and goes LOW when V2 is less than
V
TRIP2
. There is no power-up reset delay circuitry on this
pin. The V2RO pin requires the use of an external “pull-up” resistor.
Supply Voltage.
No Connect.
5
V3RO
7
WP
8
9
10
11
12
13
14
15
16
17
SCL
SDA
Vss
R
L1
R
w1
R
H1
R
H0
R
W0
R
L0
V2
18
20
6, 19
V2RO
Vcc / V1
NC
4
FN8208.2
September 7, 2010
X9522
SCL
SDA
Data Stable
Figure 1.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Data Change
Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH. The STOP condition is also
used to place the device into the Standby power
mode after a read sequence. A STOP condition can
only be issued after the transmitting device has
released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the
receiving device as the receiver. The device con-
trolling the transfer is called the master and the
device being controlled is called the slave. The
master always initiates data transfers, and pro-
vides the clock for both transmit and receive oper-
ations. Therefore, the X9522 operates as a slave in
all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software conven-
tion used to indicate a successful data transfer. The
transmitting device, either master or slave, will
release the bus after transmitting eight bits. During
the ninth clock cycle, the receiver will pull the SDA
line LOW to ACKNOWLEDGE that it received the
eight bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE
after recognition of a START condition if the cor-
rect Device Identifier bits are contained in the
Slave Address Byte. If a write operation is
selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subse-
quent eight bit word.
In the read mode, the device will transmit eight
bits of data, release the SDA line, then monitor the
line for an ACKNOWLEDGE. If an ACKNOWLEDGE
is detected and no STOP condition is generated by
the master, the device will continue to transmit
data. The device will terminate further data trans-
missions if an ACKNOWLEDGE is not detected.
The master must then issue a STOP condition to
place the device into a known state.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW. SDA state changes while SCL is
HIGH are reserved for indicating START and STOP
conditions. See Figure 1. On power-up of the
X9522, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condi-
tion, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The device continuously moni-
tors the SDA and SCL lines for the START condi-
tion and does not respond to any command until
this condition has been met. See Figure 2.
SCL
SDA
Start
Figure 2.
5
Stop
Valid Start and Stop Conditions
FN8208.2
September 7, 2010
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