PIC18C658/858
PIC18C658/858 Rev. C3 Silicon/Data Sheet Errata
The PIC18C658/858 parts you have received conform
functionally to the Device Data Sheet (DS30475A),
except for the anomalies described below.
All the problems listed here will be addressed in future
revisions of the PIC18C658/858 silicon.
Date Codes that pertain to this issue:
ALL
Note:
When the manufacture date of a newer
version of silicon is in production, the last
date where this issue may occur will be
specified.
1. Module: CAN
The CAN module may send a passive error flag
earlier than expected. This will occur at the transi-
tion point of error active to error passive, TEC
(Transmit Error Count), or REC (Receive Error
Count)
≥
128.
Work around
None for current silicon revision. Use the latest
silicon revision when it becomes available.
3. Module: LVD
The minimum and maximum LVD voltage levels
(parameter D420) have changed. The new values
are shown in Table 1.
Work around
None
Date Codes that pertain to this issue:
ALL
Note:
When the manufacture date of a newer
version of silicon is in production, the last
date where this issue may occur will be
specified.
2. Module: CAN
The CAN module may not synchronize correctly if
there is a phase error between nodes that is equal
to the Synchronization Jump Width (SJW). As a
result, the module may request retransmission of
messages from the transmitting node.
Work around
1.
2.
Use the longest SJW possible that will work
with the application.
Use the latest silicon revision when it becomes
available.
TABLE 1:
Param No.
D420
LVD MINIMUM VOLTAGES
Symbol
V
LVD
Characteristic
LVD Voltage
LVDL<3:0> =
0100
LVDL<3:0> =
0101
LVDL<3:0> =
0110
LVDL<3:0> =
0111
LVDL<3:0> =
1000
LVDL<3:0> =
1001
LVDL<3:0> =
1010
LVDL<3:0> =
1011
LVDL<3:0> =
1100
LVDL<3:0> =
1101
LVDL<3:0> =
1110
Min.
2.35
2.55
2.64
2.83
3.11
3.29
3.39
3.58
3.77
3.95
4.23
Max.
2.80
3.02
3.14
3.37
3.71
3.93
4.04
4.26
4.49
4.71
5.05
Units
V
V
V
V
V
V
V
V
V
V
V
2003 Microchip Technology Inc.
DS80126C-page 1
PIC18C658/858
4. Module: BOR
The minimum and maximum BOR Voltage levels
(parameter D005) have changed. The new values
are shown in Table 2 (below).
Work around
None.
Date Codes that pertain to this issue:
ALL
Note:
When the manufacture date of a newer
version of silicon is in production, the last
date where this issue may occur will be
specified.
6. Module: CAN
Two of the Receive Buffer modes defined by bits
RXM1 and RXM0 of the RXB0CON register
(RXB0CON<6:5>), are currently reversed from
their description in the original Device Data Sheet
(DS30475A). The actual values for these bits are
shown in the excerpt from Register 17-12 (below)
(changes from the original data sheet in
bold).
This anomaly is particular to this silicon revision.
Future revisions will restore the operation of these
bits to their original description in the Device Data
Sheet (DS30475A).
Work around
1.
Always configure the mode for Receive
Buffer 0 as ‘Receive All Valid Messages’ (bits
RXM1:RXM0 =
00).
In addition, use the
EXIDEN bit of the RXF0SIDL register
(RXF0SIDL<3>) to set the filter for standard or
extended ID messages. Set EXIDEN (=
1)
for
extended ID messages, and clear EXIDEN for
standard ID messages.
Use the latest silicon revision when it becomes
available.
5. Module: Watchdog Timer
After the WDT is allowed to time-out, all subse-
quent WDT periods following the very first, may
double in duration. This can occur if the
CLRWDT
instruction is not executed prior to the timer timing
out.
Work around
Always execute the
CLRWDT
instruction prior to
entering a potential WDT time-out condition.
2.
TABLE 2:
Param No.
D005
BOR MAXIMUM VOLTAGES
Symbol
V
BOR
BOR Voltage
Characteristic
BORV<1:0> =
11
BORV<1:0> =
10
BORV<1:0> =
01
BORV<1:0> =
00
Min.
2.35
2.55
3.95
4.23
Max.
2.80
3.02
4.71
5.05
Units
V
V
V
V
REGISTER 17-12: RXB0CON - RECEIVE BUFFER 0 CONTROL REGISTER
bit 6-5
RXM1:RXM0:
Receive Buffer Mode bits
11
= Receive all messages (including those with errors)
10
= Receive only valid messages with standard identifier
01
= Receive only valid messages with extended identifier
00
= Receive all valid messages
7. Module: WDT
When the device is configured for either EC or RC
Oscillator modes, with the Power-up Timer
enabled, bit TO of the RCON register (RCON<3>)
may default to ‘0’, even though no WDT time-out
has occurred.
The TO bit functions normally in all other
configurations.
Work around
1.
Use bit TO in conjunction with bit POR
(RCON<1>), to determine if a RESET
condition has occurred.
Use the latest silicon revision when it becomes
available.
2.
DS80126C-page 2
2003 Microchip Technology Inc.
PIC18C658/858
8. Module: I/O (Parallel Slave Port)
The Input Buffer Status bit of the PSPCON register
(PSPCON<7>) may be inadvertently cleared,
even when the PORTD input buffer has not been
read. This will occur only when the following two
conditions occur simultaneously:
•
The four Least Significant bits of the
BSR register are equal to 0Fh
(BSR<3:0> =
1111),
and
Any instruction that contains 83h in its
8 Least Significant bits (i.e., register file
addresses, literal data, address offsets,
etc.) is executed.
Work around
1.
Always disable low priority interrupts before
disabling high priority interrupts. Re-enable
the low priority interrupts afterwards, if
necessary.
Use the latest silicon revision when it becomes
available.
2.
•
10. Module: I/O (PORTB
Interrupt-on-Change)
The RB Port Change Flag bit of the INTCON reg-
ister (RBIF, INTCON<0>) may be inadvertently
cleared, even when the PORTB<7:4> pins have
not been read. This will occur only when the follow-
ing two conditions occur simultaneously:
•
The four Least Significant bits of the
BSR register are equal to 0Fh
(BSR<3:0> =
1111),
and
Any instruction that contains 81h in its
8 Least Significant bits (i.e., register file
addresses, literal data, address offsets,
etc.) is executed.
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh. In addition
to those proposed below, other solutions may exist.
1.
When developing or modifying code, keep
these guidelines in mind:
•
Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
Do not set the BSR to point to Bank 15
(BSR = 0Fh).
Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be
done through the Access Bank. Con-
tinue to use the BSR to select Banks 1
through 5 and the upper half of Bank 0.
•
•
•
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh. In addition
to those proposed below, other solutions may exist.
1.
When developing or modifying code, keep
these guidelines in mind:
•
Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
Do not set the BSR to point to Bank 15
(BSR = 0Fh).
Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be
done through the Access Bank. Con-
tinue to use the BSR to select Banks 1
through 5, and the upper half of Bank 0.
2.
If accessing a part of Bank 15 is required and
the use of Access Banking is not possible,
consider using indirect addressing.
If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
instructions contains 83h in the 8 Least Signif-
icant bits while the BSR points to Bank 15
(BSR = 0Fh).
2.
•
•
3.
9. Module: Interrupts
High priority interrupts may become improperly
enabled, while low priority interrupts become
improperly disabled at the same time. This may
occur when low priority interrupts are in an
enabled state and the following conditions occur
simultaneously:
•
•
High priority interrupts are being changed
from an enabled to a disabled state; and
One or more low priority interrupts occur.
If accessing a part of Bank 15 is required and
the use of Access Banking is not possible,
consider using indirect addressing.
If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
instructions contain 81h in the 8 Least Signifi-
cant bits, while the BSR points to Bank 15
(BSR = 0Fh).
3.
2003 Microchip Technology Inc.
DS80126C-page 3
PIC18C658/858
11. Module: Interrupts
When an interrupt occurs simultaneously with the
clearing of one or more interrupt enable flags in the
INTCON, PIE1 or PIE2 registers, the instruction
immediately following the interrupted instruction
may be executed before vectoring to the Interrupt
Service Routine (ISR). If that instruction is a con-
trol operation, the ISR may not execute as
intended.
In the case of conditional branch instructions, the
first instruction of the ISR may be skipped if the
tested condition would have resulted in a branch.
In the case of
GOTO, CALL,
or
BRA
instructions,
program execution may vector to the address
encoded in the instruction; the ISR will not be exe-
cuted at all. The GIE bit will still be cleared,
disabling all interrupts.
Additionally, on return from the interrupt (by exe-
cuting
RETFIE),
the instruction following the
interrupted instruction may be executed again.
There may be other interrupt related symptoms.
Work around
Three possible solutions are presented here.
Other solutions may exist. None of these require
special attention when setting interrupt enable bits.
1. All instructions that clear interrupt enable bits
should be followed by a
NOP
instruction.
2. Prior to disabling any interrupt source, disable
all interrupts by clearing the GIE bit
(INTCON<7>). After disabling the desired
interrupts, re-enable all interrupts by setting
GIE.
3. If interrupt priority is being used:
a) clear both GIEL and GIEH (in order) bits
(INTCON<7:6>) to disable all peripheral
interrupts
b) clear the desired interrupt enable bits
c) set both GIEH and GIEL, in order to re-enable
peripheral interrupts
12. Module: CAN Module
Under certain circumstances, the module may
transmit unexpected messages. This will only hap-
pen when all of the following conditions occur
simultaneously:
1.
2.
3.
The identifier registers for Transmit buffer
TXB0 are never used or written to;
Either of the transmit buffers, TXB1 or TXB2,
are in use; and
The CAN module attempts to retransmit a
message that has lost one or more previous
arbitrations.
Work around
Clear the TXB0SIDL and TXB0SIDH registers as
part of the CAN initialization routine.
13. Module: A/D (External Voltage Reference)
and Comparator Voltage
Reference
When the external voltage reference, V
REF
-, is
selected for use with either the A/D or comparator
voltage reference, AV
SS
is connected to V
REF
- in
the comparator module. If V
REF
- is a voltage other
than AV
SS
(which must be tied externally to V
SS
),
excessive current will flow into the V
REF
- pin.
Work around
If external V
REF
- is used with a voltage other than
0V, enable the comparator voltage reference by
setting the CVREN bit in the CVRCON register.
This disconnects V
REF
- and AV
SS
within the
comparator module.
DS80126C-page 4
2003 Microchip Technology Inc.
PIC18C658/858
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS30475A), the following
clarifications and corrections should be noted.
2. Module: LVD
Table 25-1 of the Device Data Sheet is amended
to include parameters D421, D422, D423 and
D425, related to the performance of the Low
Voltage Detect module.
In addition, the minimum and maximum LVD volt-
age levels (specification D420) are also amended
(see Issue 3 of this Errata), and typical voltage
levels are provided.
Table 25-1 should read as follows (changes and
additions in
bold):
1. Module: Timer1
Section 11.1 (Timer1 Operation) is amended with
the following clarification:
When Timer1 is configured to operate as an asyn-
chronous counter, care must be taken that there is
no incoming pulse while the module is being
turned off. If an incoming pulse arrives while
Timer1 is being turned off, the value of register
TMR1 may become unpredictable.
If an application requires that Timer1 be turned off
and if it is possible that Timer1 may receive an
incoming pulse while being turned off, synchronize
the external clock first, by clearing the T1SYNC bit
of register T1CON. Please note that this may
cause Timer1 to miss up to one count.
TABLE 25-1:
LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C
≤
T
A
≤
+85°C for industrial
-40°C
≤
T
A
≤
+125°C for extended
Param
Symbol
No.
D420
V
LVD
Characteristic
LVDL<3:0> =
0100
LVDL<3:0> =
0101
LVDL<3:0> =
0110
LVDL<3:0> =
0111
LVDL<3:0> =
1000
LVDL<3:0> =
1001
LVDL<3:0> =
1010
LVDL<3:0> =
1011
LVDL<3:0> =
1100
LVDL<3:0> =
1101
LVDL<3:0> =
1110
Supply Current
Internally Generated
Reference Voltage
LVD Voltage
Min.
2.35
2.55
2.64
2.83
3.11
3.29
3.39
3.58
3.77
3.95
4.23
—
TBD
Typ
2.58
2.78
2.89
3.1
3.41
3.61
3.72
3.92
4.13
4.33
4.64
35
1.22
Max.
2.80
3.02
3.14
3.37
3.71
3.93
4.04
4.26
4.49
4.71
5.05
50
TBD
Units
V
V
V
V
V
V
V
V
V
V
V
µA
V
Conditions
D421
D425
∆I
LVD
V
BG
2003 Microchip Technology Inc.
DS80126C-page 5
Embedded System
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