33C108
1 Megabit (128K x 8-Bit) CMOS
SRAM
Memory
Functional Block Diagram
F
EATURES
:
• R
AD
-P
AK
® Technology radiation-hardened against natural
space radiation
• 128K x 8 bit organization
• Total dose hardness:
- > 100 krad (Si)
- dependent upon space mission
• Excellent Single Event Effects:
- SEL
TH
: No LU > 68 MeV/mg/cm
2
- SEU
TH
: < 3 MeV/mg/cm
2
• Package:
- 32-Pin R
AD
-P
AK
® flat pack
• Fast access time:
- 20, 25 and 30 ns maximum times available
• Single 5V + 10% power supply
• Fully static operation
- No clock or refresh required
• Three state outputs
• TTL compatible inputs and outputs
• Low power:
- Standby: 60mA (TTL) and 10mA (CMOS)
- Operation: 180mA (20ns), 170mA (25ns) and
160mA (30ns)
D
ESCRIPTION
:
Maxwell Technologies’ 33C108 high-density 1 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance. Using Maxwell’s radiation-hardened R
AD
-P
AK
®
packaging technology, the 33C108 realizes a higher density,
higher performance, and lower power consumption. Its fully
static design eliminates the need for external clocks, while the
CMOS circuitry reduces power consumption and provides
higher reliability. The 33C108 is equipped with eight common
input/output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention. The
33C108 features the same advanced 128K x 8 SRAM, high-
speed, and low-power demand as the commercial counter-
part.
Maxwell Technologies' patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
06.14.02 Rev 2
All data sheets are subject to change without notice
1
(619) 503-3300- Fax: (619) 503-3301 - www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) CMOS SRAM
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
12-5, 27, 26, 23, 25, 4, 28, 3,
31, 2
29
22
24
13-15, 17-21
32
16
1, 30
S
YMBOL
A0-A16
WE
CS
OE
I/O 1-I/O 7
V
CC
V
SS
NC
D
ESCRIPTION
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power (+5.0V)
Ground
No Connection
33C108
Memory
06.14.02 Rev 2
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) CMOS SRAM
T
ABLE
2. 33C108 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Thermal Impedance
S
YMBOL
V
IN
, V
OUT
V
CC
P
D
T
S
T
A
Tjc
M
IN
-0.5
-0.5
--
-65
-55
--
M
AX
33C108
U
NIYS
V
V
W
°C
°C
°C/W
V
CC
+0.5V
7.0
1.0
+150
+125
6.04
T
ABLE
3. 33C108 R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Ground
Input High Voltage
1
Input Low Voltage
2
1. V
IH
(min) = +2.0V AC (pulse width < 10 ns) for I < 20 mA.
2. V
IL
(min) = -2.0V AC (pulse width < 10 ns) for I < 20 mA.
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
4.5
0
2.2
-0.5
M
AX
5.5
0
V
CC
+ 0.5
0.8
U
NITS
V
V
V
V
Memory
T
ABLE
4. 33C108 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 4.5 to 5.5V; V
SS
= 0 V; T
A
= -55 to +125°C, unless otherwise specified)
P
ARAMETER
Input Leakage Current V
IN
= V
SS
to V
CC
Output Leakage Current
CS = V
IH
, V
OUT
= V
SS
to V
CC
Output Low Voltage, I
OL
= 8 mA
Output High Voltage, I
OH
= -4 mA
Average Operating Current
Min cycle, 100% Duty CS =V
IL
, I
OUT
= 0mA V
IN
= V
IH
or V
IL
-20
-25
-30
Standby Power Supply Current
CS= V
IH
, cycle time > 25ns
CMOS Standby Current
CS > V
CC
- 0.2V, f = 0 MHz, V
IN
> V
CC
- 0.2V orV
IN <
0.2V
S
UBGROUPS
1, 2, 3
1, 2, 3
S
YMBOL
I
LI
I
LO
M
IN
-2
-2
M
AX
2
2
U
NITS
µA
µA
1, 2, 3
1, 2, 3
1, 2, 3
V
OL
V
OH
I
CC
--
2.4
0.4
--
V
V
mA
--
--
--
1, 2, 3
ISB
--
180
170
160
60
mA
1, 2, 3
I
SB1
10
06.14.02 Rev 2
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) CMOS SRAM
T
ABLE
5. 33C108 F
UNCTIONAL
D
ESCRIPTION
CS
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
33C108
S
UPPLY
C
URRENT
ISB, ISB1
I
CC
I
CC
I
CC
T
ABLE
6. 33C108 AC E
LECTRICAL
C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 4.5 to 5.5V; V
SS
= 0 V; T
A
= -55 to +125°C, unless otherwise specified)
P
ARAMETER
Read Cycle Time
-20
-25
-30
Address Access Time
-20
-25
-30
Chip Select Access Time
-20
-25
-30
Output Enable to Output Valid
-20
-25
-30
Chip Select to Output in Low-Z
1
-20
-25
-30
Output Enable to Output in Low-Z
1
-20
-25
-30
Chip Deselect to Output in High-Z
1
-20
-25
-30
Output Disable to Output in High-Z
1
-20
-25
-30
S
UBGROUPS
9, 10, 11
S
YMBOL
t
rc
20
25
30
9, 10, 11
t
AA
--
--
--
9, 10, 11
t
CO
--
--
--
9, 10, 11
t
OE
--
--
--
9, 10, 11
t
LZ
--
--
--
9, 10, 11
t
OLZ
--
--
--
9, 10, 11
t
HZ
--
--
--
9, 10, 11
t
OHZ
--
--
--
5
6
8
--
--
--
5
6
8
--
--
--
ns
0
0
0
--
--
--
ns
3
3
3
--
--
--
ns
--
--
--
10
12
14
ns
--
--
--
20
25
30
ns
--
--
--
20
25
30
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NITS
ns
Memory
06.14.02 Rev 2
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.