This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V ±5%, T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
V
CC
4.75
High-Level
V
IH
2.2
Input Voltage
Low-Level
V
IL
-0.3
Input Voltage
Input-Leakage
-1.0
I
I
0.0V
≤
V
I
≤
V
CC
Current
V
CC
= Max; Freq =
Active Current
I
CC
1MHz
High-Level
V
CC
= Min; V
OH
= 4
I
OH
Output Current
Low-Level
V
CC
= Min; V
OL
= 0.5
12
I
OL
Output Current
TYP
5.00
MAX
5.25
V
CC
+
0.3
0.8
1.0
30
50
-1
UNITS
V
V
V
μA
mA
mA
mA
6, 8
NOTES
5
5
5
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V ±5%, T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
20% of
Input
t
WI
Tap 5
Pulse Width
t
PLH
+25°C 5V
-2
Input-to-Tap
0°C to +70°C
-3
t
PLH,
Delay Tolerance
t
PHL
(Delays
≤
40ns)
-40°C to +85°C
-4
+25°C 5V
Input-to-Tap
Delay Tolerance
(Delays > 40ns)
Power-Up Time
Input Period
t
PLH,
t
PHL
t
PU
Period
0°C to +70°C
-40°C to +85°C
-5
-8
-13
2(t
WI
)
TYP
MAX
UNITS
ns
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+2
+3
+4
+5
+8
+13
200
ns
ns
ns
%
%
%
μs
ns
NOTES
9
1, 3, 4, 7
1, 2, 3, 4,
7
1, 2, 3, 4,
7
1, 3, 4, 7
1, 2, 3, 4,
7
1, 2, 3, 4,
7
9
CAPACITANCE
(T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Input Capacitance
C
IN
MIN
TYP
5
MAX
10
UNITS
pF
NOTES
2 of 7
DS1100
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and
trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
temperature range, and a supply-voltage range of 4.75V to 5.25V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if
TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
4) Intermediate delay values are available on a custom basis. For further information, email the factory
at
custom.oscillators@maxim-ic.com.
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See
Test Conditions
section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher I
CC
values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
3 of 7
DS1100
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100.
The input waveform is produced by a precision-pulse generator under software control. Time delays are
measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap
is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
+25°C
±3°C
5.0V
±0.1V
High = 3.0V
±0.1V
Low = 0.0V
±0.1V
50Ω max
3.0ns max (measured between 0.6V and 2.4V)
500ns (1μs for
-500 version)
1μs (2μs for
-500 version)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
Note: Above conditions are for test only and do not restrict the operation of the device under other
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