HEF4517B
Dual 64-bit static shift register
Rev. 7 — 11 November 2011
Product data sheet
1. General description
The HEF4517B consists of two identical, independent 64-bit static shift registers. Each
register has separate clock (nCP), data input (nD), parallel input-enable/output-enable
(nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to
nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of
the clock, regardless of the state of nPE/OE.
When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.
When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit
shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the
clock input makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C
Type number
HEF4517BP
HEF4517BT
Package
Name
DIP16
SO16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 7.5 mm
Version
SOT38-4
SOT162-1
NXP Semiconductors
HEF4517B
Dual 64-bit static shift register
4. Functional diagram
7
4
1D
1CP
64-BIT STATIC SHIFT REGISTER
3
1PE/OE
INPUT/3-STATE-OUTPUT CIRCUITRY
1Q64
1Q48
1Q32
1Q16
5
2
6
1
9
12
2D
2CP
64-BIT STATIC SHIFT REGISTER
13
2PE/OE
INPUT/3-STATE-OUTPUT CIRCUITRY
2Q64
2Q48
2Q32
2Q16
11
14
10
15
001aae694
Fig 1.
Functional diagram
HEF4517B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 11 November 2011
2 of 16
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Product data sheet
Rev. 7 — 11 November 2011
3 of 16
HEF4517B
NXP Semiconductors
1D
D
CP
FF 1
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
FF 16
FF 17
FF 32
FF 33
FF 48
FF 49
FF 64
1CP
1PE/OE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
1Q16
1Q32
1Q48
1Q64
2D
D
CP
FF 1
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
D
CP
O
FF 16
FF 17
FF 32
FF 33
FF 48
FF 49
FF 64
2CP
Dual 64-bit static shift register
2PE/OE
HEF4517B
2Q16
2Q32
2Q48
2Q64
001aae696
Fig 2.
Logic diagram
NXP Semiconductors
HEF4517B
Dual 64-bit static shift register
5. Pinning information
5.1 Pinning
HEF4517B
1Q16
1Q48
1PE/OE
1CP
1Q64
1Q32
1D
V
SS
1
2
3
4
5
6
7
8
001aae695
16 V
DD
15 2Q16
14 2Q48
13 2PE/OE
12 2CP
11 2Q64
10 2Q32
9
2D
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
1Q16, 2Q16
1Q48, 2Q48
1PE/OE, 2PE/OE
1CP, 2CP
1Q64, 2Q64
1Q32, 2Q32
1D, 2D
V
SS
V
DD
Pin description
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
3-state input/output
3-state input/output
parallel input-enable/output-enable input
clock input
3-state input/output
3-state input/output
data input
ground supply voltage
supply voltage
HEF4517B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 11 November 2011
4 of 16
NXP Semiconductors
HEF4517B
Dual 64-bit static shift register
6. Functional description
Table 3.
Inputs
nCP nD
nPE/OE
data entered L
into 1st bit
data entered H
into 1st bit
X
X
L
H
Function table
[1]
Inputs/outputs
nQ16
content of
16th bit
displayed
data at nQ16
entered into
17th bit
no change
Z
nQ32
content of
32nd bit
displayed
data at nQ32
entered into
33rd bit
no change
Z
nQ48
content of
48th bit
displayed
data at nQ48
entered into
49th bit
no change
Z
nQ64
content of
64th bit
displayed
One 64-bit shift register. The
content of the shift register is
shifted over one stage
Mode
remains in ‘Z’ Four 16-bit shift register. The
state
content of the shift registers is
shifted over one stage
no change
Z
no change
no change
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state;
= positive-going transition;
= negative-going transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+85
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
DIP16 package
SO16 package
per output
[1]
[2]
-
-
-
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
HEF4517B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 11 November 2011
5 of 16