75i
CY7C375i
UltraLogic™ 128-Macrocell Flash CPLD
Features
•
•
•
•
128 macrocells in eight logic blocks
128 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR™) Flash technology
— JTAG Interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
— t
CO
= 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i™ family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C375i is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic™ F
LASH
370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
Logic Block Diagram
CLOCK
INPUTS INPUTS
1
INPUT
MACROCELL
4
4
INPUT/CLOCK
MACROCELLS
4
36
PIM
16
36
16
36
16
36
16
LOGIC
BLOCK
16 I/Os
I/O
112
–I/O
127
I/O
0
–I/O
15
16 I/Os
LOGIC
BLOCK
A
16 I/Os
LOGIC
BLOCK
36
16
36
16
36
16
36
16
H
LOGIC
BLOCK
16 I/Os
I/O
16
–I/O
31
B
16 I/Os
LOGIC
BLOCK
G
LOGIC
BLOCK
16 I/Os
I/O
96
–I/O
111
I/O
32
–I/O
47
C
16 I/Os
LOGIC
BLOCK
F
LOGIC
BLOCK
16 I/Os
I/O
80
–I/O
95
I/O
48
–I/O
63
D
64
E
64
I/O
64
–I/O
79
7C375i–1
Selection Guide
7C375i–125 7C375i–100 7C375i–83
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
10
5.5
6.5
125
12
6
7
125
15
8
8
125
7C375iL–83
15
8
8
75
7C375i–66 7C375iL–66
20
10
10
125
20
10
10
75
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 4, 2001
CY7C375i
Pin Configurations
(continued)
PGA
Bottom View
R
P
I/O
109
I/O
112
I/O
115
I/O
118
I/O
121
I/O
123
I/O
126
I/O
127
I/O
0
I/O
3
I/O
5
I/O
7
I/O
10
I/O
11
I/O
14
I/O
106
I/O
110
I/O
113
I/O
108
I/O
111
/SDI
I/O
104
I/O
107
I/O
116
I/O
119
I/O
122
I/O
125
GND
I/O
1
I/O
4
I/O
6
I/O
9
I/O
13
I/O
15
I/O
17
I/O
16
I/O
19
N
M
I/O
105
I/O
114
I/O
117
I/O
120
I/O
124
ISR
EN
I/O
2
GND
I/O
8
I/O
12
GND
I/O
102
V
CC
V
CC
GND
V
CC
GND
I/O
18
I/O
20
/SCLK
I/O
23
I/O
22
L
I/O
100
I/O
101
I/O
103
I/O
21
I/O
25
K
I/O
98
I/O
99
GND
CLK
3
/I
4
CLK
2
/I
3
I/O
92
I/O
24
I/O
26
I/O
27
J
I/O
96
I/O
97
V
CC
V
CC
CLK
28
CLK
0
/I
0
CLK1
/I1
GND
I/O
29
I/O
30
H
I/O
95
GND
GND
GND
GND
I/O
31
G
I/O
94
I/O
93
V
CC
V
CC
I/O
33
I/O
32
F
I/O
91
I/O
90
I/O
88
I/O
35
I/O
34
E
I/O
89
I/O
87
I/O
85
I/O
39
I/O
37
I/O
36
D
I/O
86
I/O
84
I/O
82
GND
I/O
76
/SDO
I/O
73
V
CC
GND
V
CC
V
CC
I/O
56
I/O
53
I/O
43
I/O
40
I/O
38
C
I/O
83
I/O
81
GND
I/O
72
GND
I/O
66
I
2
I/O
60
I/O
50
I/O
47
I/O
44
I/O
41
B
I/O
80
I/O
79
I/O
77
I/O
70
I/O
68
I/O
65
GND
I/O
61
I/O
58
I/O
55
I/O
52
/
I/O
49
SMODE
I/O
71
12
I/O
51
13
I/O
46
I/O
42
A
I/O
78
1
I/O
75
2
I/O
74
3
I/O
71
4
I/O
69
5
I/O
67
6
I/O
64
7
I/O
63
8
I/O
62
9
I/O
59
10
I/O
57
11
I/O
48
14
I/O
45
15
7C375i–4
Functional Description
(continued)
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the F
LASH
370i family, the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 128 I/O pins on the CY7C375i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C375i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
Page 4 of 17
Document #: 38-03029 Rev. **
CY7C375i
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i PLDs. Note that product term allocation is han-
dled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with F
LASH
370i.”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
CCIO
pins are connect-
ed to a 3.3V source, the input voltage levels are compatible
with both 5.0V and 3.3V systems, while the output voltage lev-
els are compatible with 3.3V systems. There will be an addi-
tional timing delay on all output buffers when operating in 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C375i is available from Cy-
press’s
Warp™, Warp
Professional™, and
Warp
Enterprise™
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most all third-party design tools. Please refer to third-party tool
support for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage .................................................... 12.5V
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
V
CCINT
5V
±
0.25V
V
CCIO
5V
±
0.25V
OR
3.3V
±
0.3V
5V
±
0.5V
OR
3.3V
±
0.3V
Industrial
−40°C
to +85°C
5V
±
0.5V
Military
[2]
–55°C to +125°C
5V
±
0.5V
Note:
2. T
A
is the “instant on” case temperature.
Document #: 38-03029 Rev. **
Page 5 of 17
京公网安备 11010802033920号
EEWORLD
