531UB449M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531UB449M000DGR

531UB449M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 449MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531UB449M000DGR Overview

CMOS/TTL Output Clock Oscillator, 449MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UB449M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	449 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Mobile phone camera flash control circuit

Production of high-quality active two-way constant current power amplifier 01

Aoqi SJ-902 food mixer circuit diagram

Low power consumption 12V power supply circuit diagram

point signal generator

About WINCE SDK provided by Microsoft: I am going to develop a simple program on a PDA, and I don't plan to customize the wince SDK myself. I saw the Pocket PC 2003 provided by Microsoft in the reference book, and I plan to use it. However...; hustxsh Embedded System

RMS calculation of non-sinusoidal signal in FPGA?: Due to project requirements, I need to find the effective value of a digital sine wave signal with many harmonics. The method I have thought of now is to collect the signal, filter the high-order harm...; eeleader FPGA/CPLD

LED Applications-1 Line Control & AN033: [i=s]This post was last edited by dontium on 2015-1-23 13:13[/i]LED Application Manual1-wire control – eliminates microprocessor control of LED drivers AN033 -- Converting the RF Flash LED Software Ex...; 德州仪器 Analogue and Mixed Signal

The top ten bad behaviors that men should not have: 1. Make a V sign when taking a photo: Oh my god, please save this old-fashioned person! Even if you stand like a wooden stake. 2. Idol worship: There are no idols anymore, only "objects to vomit". 3. ...; simonprince Talking

STM8S103 read protection drives me crazy: I made 6 samples for the customer, burned the software with STVP, and selected the READONLY protection option.A few days ago, the customer sent 6 boards to me for modification. It turned out that 4 bo...; ljxh401 stm32/stm8

An error in running Nios IDE: When the LED marquee program in IDE is running, the following error message always appears: nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]",...; hd12 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components