Features
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8032 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes RAM
Full duplex UART
Asynchronous port reset
6 sources, 2 level interrupt structure
64 Kbytes program memory space
64 Kbytes data memory space
Power Control modes
Idle mode
Power-down mode
On-chip oscillator
Operating Frequency: 30 MHz
Power supply: 4.5-5.5V
Temperature range: Military (-55 to 125
o
C)
Packages: Side Brazed 40-pin, MQFPJ 44-pin
QML Q and V with SMD 5962-00518
SCC C an B with specification SCC9521002
Rad Tolerant
8-bit ROMless
Microcontroller
80C32E
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit
microcontroller.
The 80C32E retains all the features of the 80C32 with 256K bytes of internal RAM, a
6-source, 2-level interr upt system, an on-chip oscillator and three 16-bit
timer/counters.
The fully static design of the 80C32E allows to reduce system power consumption by
bringing the clock frequency down to any value, even DC, without loss of data.
The 80C32E has 2 software-selectable modes of reduced activity for further reduction
in power consumption. In the idle mode the CPU is frozen while the timers, the serial
port and the interrupt system are still operating. In the power-down mode the RAM is
saved and all other functions are inoperative.
Rev. K – 21-Aug-01
1
Pin Description
MNEMONIC
V
SS
V
CC
Type
I
I
Ground:
0V reference
Power Supply:
This is the power supply voltage for normal, idle and power-down
operation
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal pull-
up when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
SS
permits a power-on reset
using only an external capacitor to V
CC.
Address Latch Enable:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory.
Program Store ENable:
The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
Name and Function
P0.0-P0.7
I/O
P1.0-P1.7
I/O
P2.0-P2.7
I/O
I/O
I
O
P3.0-P3.7
I
I
I
I
O
O
RST
I
ALE
O (I)
PSEN
O
4
80C32E
Rev. K – 21-Aug-01
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